using NAND gate to create square pulse

Thread Starter

minhduc515

Joined Jun 15, 2017
3
I am trying to create a digital clock, using 74ls90,74ls47

I have some question when trying to create 1 Hz square pulse

This picture is my teachers's simulation


I have searched on internet, and i known that i can use Ne555, or crystal, but i can't find any document about using NAND gate to create pulse

Anyone can help me explain that circuit ? And how i can choose value of resistor, capacitor ? (eg :R43 = 4k7, R44 = 1k, C3 = 100uF ..)

Sorry for my bad English :D
 

EM Fields

Joined Jun 8, 2016
583
I am trying to create a digital clock, using 74ls90,74ls47

I have some question when trying to create 1 Hz square pulse

This picture is my teachers's simulation


I have searched on internet, and i known that i can use Ne555, or crystal, but i can't find any document about using NAND gate to create pulse

Anyone can help me explain that circuit ? And how i can choose value of resistor, capacitor ? (eg :R43 = 4k7, R44 = 1k, C3 = 100uF ..)

Sorry for my bad English :D
https://www.fairchildsemi.com/application-notes/AN/AN-118.pdf
 

Bordodynov

Joined May 20, 2015
2,420
I made this scheme to show the error of simulation of logic circuits in analog devices. Usually models of logic chips are built on digital elements with great simplification of properties of real elements. This speeds up the simulation, but may not reflect reality. This is especially true for TTL circuits.
 

djsfantasi

Joined Apr 11, 2010
5,704
The two NAND gates, along with the resistors and capacitor, form a common circuit for an oscillator or astable multivibrator.

An explanation of how this works can be found here. Click on the link.
 

DickCappels

Joined Aug 21, 2008
5,944
The bit of information that might be missing is that the nand gates in your schematic are wired to act as inverters rather than gates. Therefore explanations of the RC oscillators using inverters are applicable to your circuit.
 

Bordodynov

Joined May 20, 2015
2,420
The circuit is not symmetrical for better triggering of oscillations. In the first stage, the lower output transistor is transferred to the amplification mode. In the second cascade, the Darlington is translated into the amplification mode. The circuit works without this resistor.
Here you can play:
 

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Bordodynov

Joined May 20, 2015
2,420
Your last schematic shows AND gates; not NAND gates... I wouldn't expect that circuit to oscillate.
In all schemes, the hierarchical block 2NAND is used. The output pin of the symbol is surrounded by a small circle. For me, this is a sign of inversion (NOT).
If you have LTspice, then you can check everything. See LS.zip.
 

djsfantasi

Joined Apr 11, 2010
5,704
In all schemes, the hierarchical block 2NAND is used. The output pin of the symbol is surrounded by a small circle. For me, this is a sign of inversion (NOT).
If you have LTspice, then you can check everything. See LS.zip.
Oops, you're correct. I missed the bubble. Sorry.
 

MrAl

Joined Jun 17, 2014
6,633
I have found this site about NAND gate waveform generator, that similar to my simulation : http://www.electronics-tutorials.ws/waveforms/generators.html

It said that the frequency of the square wave is given by f = 1 / 2.2 R1C1. But how it is derived?
Hi there,

It is derived through the use of circuit analysis, assuming some threshold values for the Schmitt Trigger gates. Notice that down the page a little they have "1.6v" and "0.8v". Those are the upper and lower threshold voltages. The gate changes state when one of those levels is reached on the input, and that starts the next half cycle.

If we look at this in somewhat simple terms with the output going to nearly zero for a low and to nearly Vcc for a high, we have two maiin equations:
Discharging: Vc(t)=Vc0*e^(-t/RC)
Charging: Vc(t)=(Vcc-Vc0)*(1-e^(-t/RC))+Vc0

These two are solved for t and that yields two different values for t we can call t1 and t2, then the total time is:
t_total=t1+t2
and so the frequency is:
f=1/(t1+t2)

So after solving these we get the true frequency.
Since the cap voltage Vc0 is the lower threshold when it starts to charge and the cap voltage Vc0 is the upper threshold when it starts to discharge, we have:
Discharging: Vc(t)=VH*e^(-t/RC)
Charging: Vc(t)=(Vcc-VL)*(1-e^(-t/RC))+VL

where VH and VL are the high and low thresholds respectively.

Also, since the charge time goes from VL to VH and discharge from VH to VL, we have:
Discharging: VL=VH*e^(-t/RC)
Charging: VH=(Vcc-VL)*(1-e^(-t/RC))+VL

so the only variable left in each equation is the time t.
You can try to solve those if you like and that will show you the true frequency. See if it matches their claim. It probably will not because they often use approximations found elsewhere that they did not check before creating their web pages.
 
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