# Logic Diagram using 4-bit Parallel Adder and NAND Gate

#### Eehit

Joined Nov 1, 2020
4
How to design a multiply-by-6 circuit given a 3-bit binary unsigned value ABC as its input. The circuit generates a 5-bit binary number S4 S3 S2 S1 S0, and an output V.
Since the circuit may not accommodate certain input value owing to the limited number of output bits, such an input value is deemed invalid, and the corresponding output will be don’t-care values. The output V is used to indicate whether the input value is valid or not: 1 if the input value is valid, or 0 otherwise.

#### ericgibbs

Joined Jan 29, 2010
18,234
hi Eehit,
Welcome to AAC.
E

• Eehit

#### Eehit

Joined Nov 1, 2020
4
So I am not able to figure out how to use the 4 bit parallel adder and the NAND gate to perform multiply by 6 operation. I have been able to solve the truth table and SOP expressions for each of S0, S1, S2, S3, S4. But I am just not able to think how to design this multiply by 6 circuit... I also thought about using this concept like:-

Suppose I have X as my input. Then I shift the binary input of X by one place which shall make it 2X. I shall then add another X to 2X to make it 3X. Then I shall again shift the binary number 3X by one place to make it 6X. This way it will get multiplied to six times.

#### dl324

Joined Mar 30, 2015
16,146
Welcome to AAC!

Please post the entire text of the problem.

#### WBahn

Joined Mar 31, 2012
29,510
So I am not able to figure out how to use the 4 bit parallel adder and the NAND gate to perform multiply by 6 operation. I have been able to solve the truth table and SOP expressions for each of S0, S1, S2, S3, S4. But I am just not able to think how to design this multiply by 6 circuit... I also thought about using this concept like:-

Suppose I have X as my input. Then I shift the binary input of X by one place which shall make it 2X. I shall then add another X to 2X to make it 3X. Then I shall again shift the binary number 3X by one place to make it 6X. This way it will get multiplied to six times.
What you have described here does not produce the required V output.

#### Eehit

Joined Nov 1, 2020
4
You are to design a multiply‐by‐6 circuit given a 3‐bit binary unsigned value ABC as its input. The circuit generates a 5‐bit binary number S4 S3 S2 S1 S0, and an output V. Since the circuit may not accommodate certain input value owing to the limited number of output bits, such an input value is deemed invalid, and the corresponding output will be don’t‐care values. The output V is used to indicate whether the input value is valid or not: 1 if the input value is valid, or 0 otherwise.
Let's implement the multiply‐ by‐6 circuit using a 4‐bit cascade adder (parallel adder). The 4‐bit adder is used to generate the 5‐bit outputS4S3S2S1S0. [ Hint: Think in binary]
For the output V, you are to use a NAND gate to implement it.

#### Eehit

Joined Nov 1, 2020
4
Welcome to AAC!

Please post the entire text of the problem.
You are to design a multiply‐by‐6 circuit given a 3‐bit binary unsigned value ABC as its input. The circuit generates a 5‐bit binary number S4 S3 S2 S1 S0, and an output V. Since the circuit may not accommodate certain input value owing to the limited number of output bits, such an input value is deemed invalid, and the corresponding output will be don’t‐care values. The output V is used to indicate whether the input value is valid or not: 1 if the input value is valid, or 0 otherwise.
Let's implement the multiply‐ by‐6 circuit using a 4‐bit cascade adder (parallel adder). The 4‐bit adder is used to generate the 5‐bit outputS4S3S2S1S0. [ Hint: Think in binary]
For the output V, you are to use a NAND gate to implement it.

#### WBahn

Joined Mar 31, 2012
29,510
You are given a HUGE hint and told what the NAND gate is for -- it is to implement the V output.

But forget about that for the moment, show your best attempt to implement the circuit. You've described how you would approach getting the Y = 6X output, but a sketch of the schematic you would use would be nice. Also show your best attempt to come up with the V output.

#### dl324

Joined Mar 30, 2015
16,146
Let's implement the multiply‐ by‐6 circuit using a 4‐bit cascade adder (parallel adder). The 4‐bit adder is used to generate the 5‐bit outputS4S3S2S1S0. [ Hint: Think in binary]
Are you only allowed to use 1 4-bit adder? Can you use half adders and AND gates?

#### WBahn

Joined Mar 31, 2012
29,510
Are you only allowed to use 1 4-bit adder? Can you use half adders and AND gates?
It sounds like he is expected to use exactly one 4-bit adder and exactly one two-input NAND gate. There are two ways (at least) of doing it with just those two blocks.