Designing Schmitt trigger oscillator using CMOS NAND gate.

Thread Starter

Alex_Khan

Joined May 27, 2020
44
Hello,
I am designing a Schmitt trigger oscillator based on a CMOS NAND gate. The block diagram along with schematics and its results are attached for your reference. I am using the CADENCE tool with 0.35um technology.

Question: it can be seen in the result, the charging time of the capacitor is large which affects the oscillating signal at the beginning. To reduce charging time I need to reduce the RC time constant but it affects my oscillating frequency. Once i reduce the RC time constant then i am limited to a certain oscillating frequency.

Oscillating frequency: f=1/2.2RC

How can I reduce the charging time of the cap (other than the RC time constant in my schematics) so that I get the least distortion at the initial stage of the oscillating signal?
 

Attachments

eetech00

Joined Jun 8, 2013
2,352
Hello,
I am designing a Schmitt trigger oscillator based on a CMOS NAND gate. The block diagram along with schematics and its results are attached for your reference. I am using the CADENCE tool with 0.35um technology.

Question: it can be seen in the result, the charging time of the capacitor is large which affects the oscillating signal at the beginning. To reduce charging time I need to reduce the RC time constant but it affects my oscillating frequency. Once i reduce the RC time constant then i am limited to a certain oscillating frequency.

Oscillating frequency: f=1/2.2RC

How can I reduce the charging time of the cap (other than the RC time constant in my schematics) so that I get the least distortion at the initial stage of the oscillating signal?
You would have pre-charge "C" before the oscillator is enabled.
 

Bernard

Joined Aug 7, 2008
5,788
A possibility: Use 2 charge- discharge paths with a diode in series with charge path, cathode to cap., 2 or more diodes in series with discharge path, anodes to C. Rs may need tweeking. If there is a long gap between bursts may add a large R, 10 X R ? from vdd to cap. +.
 
Last edited:

AnalogKid

Joined Aug 1, 2013
9,249
Many oscillator circuits have this problem, and almost all relaxation types do. The 555 is famous for it. One way around it is to adjust the two trip points such that one of them is at GND. In this way, zero charge on the capacitor no longer is unique to the first half-cycle starting point; it occurs at the start of every cycle. This is very difficult to do with normal digital logic circuits and only one power supply rail, but it is an indicator of what the circuit needs to do to eliminate the condition by design (as opposed to patching it with some kind of disconnectable pre-charge scheme).

You don't say what your required frequency range is. Another approach is two monostables in a circle. One of them has a fixed period that is long enough to completely discharge the second one's timing capacitor. In this way (again), each cycle has a point in it when the timing cap voltage is zero.

ak
 

dl324

Joined Mar 30, 2015
12,871
I am designing a Schmitt trigger oscillator based on a CMOS NAND gate.
Why not just design one using MOSFETs? 3 N channel and 3 P channel are all it takes.

From a Nat Semi CD40106 datasheet:
clipimage.jpg
You don't need the output buffer or the latch.
 

crutschow

Joined Mar 14, 2008
27,198
Let the oscillator run all the time, and connect the enable to the second gate.
That's a good idea.
If you don't want a shortened pulse at either the start or stop, then you could connect the enable to the D input of a D Flip-flop with the flip-flop clock connected to the oscillator signal.
The flip-flop output would then enable/disable the output signal at the clock edge, eliminating any truncated pulses.
LTspice simulation of example circuit below:

1612156584707.png
 
Last edited:

Ian0

Joined Aug 7, 2020
2,196
If you don't want a shortened pulse at either the start or stop, then you could connect the enable to the D input of a D Flip-flop with the flip-flop clock connected to the oscillator signal.
That's also a good idea! I was wondering if the random shortened pulse at beginning and end would present a problem.
 
Top