Use of ISO224 as analog isolator

Thread Starter

lean345

Joined Apr 5, 2024
5
Hi, I’m using ISO224 to isolate analog signal from a sensor (e.g. Temperature/Humidity sensor) for Raspberry Pico ADC (analog pins). As per my understanding, IC has 2 output pins (Inverting & Non-inverting). Can I use only single pin (Non-inverting) for output and ground the other so that the Gain should be unity.

Please mention if there is any other alternative ICs for the application.iso224.PNG
 

LadySpark

Joined Feb 7, 2024
194
Hi, I’m using ISO224 to isolate analog signal from a sensor (e.g. Temperature/Humidity sensor) for Raspberry Pico ADC (analog pins). As per my understanding, IC has 2 output pins (Inverting & Non-inverting). Can I use only single pin (Non-inverting) for output and ground the other so that the Gain should be unity.

Please mention if there is any other alternative ICs for the application.View attachment 322435
I wonder why you are trying to use this chip with a sensor. Also, the I/O on the raspberry pico is tied to a 3.3V supply so this chip wouldn't work. There are ones for 3.3V VDD2 but these chips are design for voltage sensing several hundred volts and not a millivolt sensor.
These were design for balanced input adc and you would have to use another op amp afterwards to convert to unbalanced.
 

Thread Starter

lean345

Joined Apr 5, 2024
5
I wonder why you are trying to use this chip with a sensor. Also, the I/O on the raspberry pico is tied to a 3.3V supply so this chip wouldn't work. There are ones for 3.3V VDD2 but these chips are design for voltage sensing several hundred volts and not a millivolt sensor.
These were design for balanced input adc and you would have to use another op amp afterwards to convert to unbalanced.
So I was at the wrong track. I just have to protect analog pins from surges. Can you please share example of a reliable protection circuit?
 

ronsimpson

Joined Oct 7, 2019
3,229
Can I use only single pin (Non-inverting) for output and ground the other so that the Gain should be unity.
No. I have used many different versions of analog isolators. Most do not have a reliable output voltage as measured from ground. For zero putout the output voltage is about 2 volts. The difference of the two outputs is zero.

I used a differential op amp to get single ended. Gain set to 1.
1715865883015.png
 

ronsimpson

Joined Oct 7, 2019
3,229
Why are the analog isolators built this way?
1) I am switching GANFETs with very fast turn on/off time. The volts/nS are very high. At the max this part can handle. The capacitance across the isolation gap causes current to flow on sharp edges. The differential outputs help subtract out the switching noise.
2) The outputs are not rail to rail. It is hard to make an op-amp that works at zero volts. The output work at 1.5 to 3.5 volts.
 

LadySpark

Joined Feb 7, 2024
194
So I was at the wrong track. I just have to protect analog pins from surges. Can you please share example of a reliable protection circuit?
Read this article on protecting ADC circuits.
https://www.analog.com/en/resources/technical-articles/protecting-adc-inputs.html
If the signal is positive going only and no negative voltage you use a pair of reversed biased diodes tied to Vcc (or positive clamping voltage) and GND. If it is anm AC signal, you have to tie the diodes to a positive and negative clamping voltage which usually either the +/- supply or a voltage drop of that supply. Also, you add a resistor the size of the load rating of the previous op amp so that there is a load for it in the event of over voltage.
 

dovo

Joined Dec 12, 2019
72
So I was at the wrong track. I just have to protect analog pins from surges. Can you please share example of a reliable protection circuit?
So you want to protect analog pins from surges. As with every design it should be begin with design specifications and with those a circuit almost designs itself. You are free to make you own specs or use an existing one such as IEC 61000-4-2 Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test. This is what consumer items you purchase (that are designed to be sold into the European Union) are designed to me. This is what I use for ESD designs.

Application note AP895 by SILICON LABS explains the test and test levels for HBM (Human Body Model) compliance. If you want the highest level of protection, design to level 4 which is 8 kV contact discharge and 15 kV air discharge. The discharge source mimics a human body by using 150 pF discharged through 330 ohms. The switch in the ESD pulser is almost always a mechanical relay. The current rise time is sub-1 nanosecond. Every IC has an HBM spec and that is often 2 kV. Some older parts are only 400 V. That is enough for product assembly but not enough for real world survivability and so we need to add external ESD protection circuitry.

A common approach is for the external ESD clamping device to take the brunt of the ESD pulse of tens of amps for tens of nanoseconds. ICs usually, but not always, have built in ESD clamp diodes that try to do the same. It becomes a contest between the added ESD clamp and the IC's internal clamp to see who can divert the most current. For this reason I place series impedance between the two to control the IC's internal clamp current. If the IC is rated for 2000V HBM we want to limit it to 2000V/330 ohms = 6 amps. A simplified ESD circuit is shown below. V1 pulses to 8 kV in 1 ns with the ESD device carrying 23 amps while the IC carries 1.3 amps. The IC survives.

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Here is the same circuit with the parasitic inductance of each component. This is a well designed SMD layout having minimum inductance. The waveform below shows IC ESD current reaching 5 amps which is bumping up against its HBM spec. Anyway, what I'm getting at with these models it can be good to add limiting resistance (R2). As with every component there is an optimum range that will do the job. For this case we find that 30 ohms is enough to protect the IC. We then figure out what is the highest resistance below at some design spec is encroached on. Hopefully there is a large gap between these two values. Sometimes I will select a value that is the geometric mean. For example, say we get 30 ohms and 1000 ohms. Below 30 ohms we exceed the ESD spec and above 1000 ohms we begin to affect input noise, offset voltage or what have you. The geometric mean of 30 and 1000 ohms is 173 ohms. I might put in a 200 ohm resistor.

We can refine the models with a model of the actual ESD device if there is a model. ICs do not come with such models and so I tend to be conservative when possible, thinking 1N4148 diodes are a good enough model. Sometimes a capacitor can be placed on the input to absorb the ESD pulse. This usually works, although there are components without ESD clamps to the rails (some DRAM). These components rely on the very high ESD dv/dt to trigger parasitic transistors to protect gate oxide. For the IC designer that is a freebee; they get ESD protection without adding capacitance or consuming die area. They actually design I/O devices to meet ESD while still doing what I/Os are supposed to do. So, slow down the ESD risetime and the component has no ESD protection.

Another gotcha on input protection is using things like zener diodes. They might protect when the IC is powered up and its internal diodes don't conduct until the zener-clamped voltage exceeds the supply rail by a diode drop. But when the IC is powered down the IC clamp diode begins to conduct at just one diode drop and the zener never turns on to protect the IC.

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https://www.silabs.com/documents/public/application-notes/AN895.pdf

https://compliancetesting.com/iec-en-61000-4-2/
 
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