I have to create a counter that does as follows:

0-1-2-3-4-5-6-7-8-9-8-7-6-5-4-3-2-1 and stops on one(displayed on seven segment)

No Programming allowed. I am using a 74192 up/down counter and a 7447 seven segment decoder as well.

So far it only: 9-8-7-6-5-4-3-2-1 and stopping

I attached my schematic. I am not sure where to go from here I am in a stand still. This project is due very soon. Can anyone offer help??

 

Hello Beenjamín

There are two things which must be taken into consideration.
One is that there are two "ones" in the sequence of numbers.
The other is that the counter will count in both directions.

The case of the "ones":
You have to detect if it is the first "one" or the second "one".
If the first "one" to continue counting upwards until 9. change the count direction and then continue to count downward until reaching the second "one". then stop.

The intention of the Flip-Flip and associated circuitry that You have in your scheme is just to change the count direction. . . . Right? ..
But apparently not doing its function.
This is a point to improve.

Suppose that when the counter starts (zero) we have Tn = 0; we know that in Tn +1 is the first "one". And in Tn + 17 we know that the second "one".
Now is the time to stop the counter.

Another idea:
If you add another counter to your circuit you can count the "ones". . . . Right?
In the second "one" it's time to stop the counter.
This counter could be done with 2 Flip-Flip's.

My recommendation is that you first make the counter to count cyclically in both directions.
once achieved, add a counter to count the "ones". At the second "one" stop the counter as shown in your diagram: with the OR gate which is connected to the pulse generator by one of its inputs

regards
at your service

 

Hello BeenJamin

Now I see that this is my circuit but mine in Proteus ISIS simulator.
I had attached it in this thread.
http://forum.allaboutcircuits.com/showthread.php?p=542674#post542674
Anyway here's the Multisim version.

Note that lacks the 74LS47 decoder, limiting resistors for Display, 7 segment display common anode.
.
I had to go with a friend to lend me his PC to develop this circuit in multisim.

Enjoy it.

 

@MrCarlos,

You are not helping the OP learn the concepts and develop the skills by just doing the work for them and giving them the solution. If that were the case, homework assignments would come with the worked solutions. Instead, ask leading questions or make suggestions to guide the person toward the right path, but please don't just give them the answer. If you do that, then don't you think YOU should get the grade for the work? More pointedly, you have now put the OP in the position of submitting YOUR work while claiming it as their own.

 

Sorry WBahn
Yes, certainly, I'm sorry, this will not happen again.

 

Live and learn, my friend. Much of your original response is quite reasonable. Just be sure to give them a chance to absorb it and work with it and come back with a revised attempt.

 

There are two decision points in the sequence. First; change from up to down when 9 is reached and second; stop when 1 is reached while counting down. It's not necessary to keep track of the number of occurances of 1, just whether 1 occurs in conjunction with down.

 

Its not necessary the problem of stopping on the one, that is working perfectly. I just cant seem to get it to count up first. Am I close with my circuitry or am I completely missing something? I seem to be running in circles over this.

 

I can't make out the pin names on your schematic. Please post one that has better resolution and contrast.

 

Here is the schematic blown up a little.

 

That's much better. Thanks.

I'm concerned about race conditions and glitches, particularly on your clock lines to the JKFF and the '192 counter. You should try to design your circuit so that there is a single clock. Then, if you have to gate it at all, you need to look very carefully to ensure that it can't glitch.

 

hmm. Im confused as to what you mean by single clock

 

also would it be easier to count to 7 instead of 9?

 

hmm. Im confused as to what you mean by single clock

Any part that has a clock input has setup and hold time requirements for the inputs to that part. If you have two parts that use different clocks, then the outputs from one part may be changing during the setup/hold time window of the other part. This results in undefined behavior of the part.

You have a situation with a circular clock. You have a 10kHz clock coming in. That is gated to produce two clocks for the counter IC. The counter IC produces a couple of outputs that are gated to produce the clock for the JKFF. The resulting outputs from the JKFF are part of the logic that gates the clock to the counter. How do you know (I mean KNOW) that there is no possibility of spurious transitions at any of the clock pins to either part?

You are operating in the world of asynchronous sequential logic and there be demons there. They can be tamed, but the threat must be honored because sometimes the dragon wins.

 

Also if I were to count to 7 would that be more simple and if I could use a GAL22v10 chip would that make it easier?

 

also would it be easier to count to 7 instead of 9?

Why do you think that?

It's very possible that you can exploit one pattern's peculiarities more easily than another's, but I would recommend designing your circuit not to do that. If you do, then what happens when the customer changes the spec at the last minute to count to 5 or some other number? You have to redesign your circuit and make sure all the changes are correct. If you've made it so that the specific value is generic, then you have to move a few very clearly identified wires (or perhaps add/remove a couple inverters, again clearly identified).

 

well the assignment is to count to 7.. but We were going to try to do 9 for extra credit.

 

but I do see your point