I am trying to build an up and down counter using d flip flops. So far this is what I have, but when i try to compile, quartus says that I am passing net more than one value. It highlights the mulitplexer and the NOT and Q value feeding it, for each D flip flop. I don't understand what I am doing wrong. Any help would be great thanks!

 

I 've never used Quartus, but I have an observation: Why is there a line crossing each NOT gate? Is it possible that this is a wire shorting it, or is it just a matter of how the gate is drawn?

 

well, i thought that's how it was drawn. I connected the wire from Q to the input of the MUX and then i placed the not on top of it. I see how I might be mistaken about that though. I'll have to fix that when I get home. Maybe that's what's wrong. Thanks.

 

so, your observation was correct. After removing the extra wire, my circuit compiled. I ran it through the simulator though, and I am not getting the right timing results. I am getting the wrong timing diagram from my timing simulation. My up counter works fine, but my Q values stay at 1 for every clock cycle as long as up/down = 1. My current design is attached. Thanks for any help.

 

I suggest you tie the Preset and Reset pins into Vcc and give it another try.

Also, how do you know that your counter works, if your Q values stay static?