Hey guys, I am writing up a report on a practical we did and am baffled by the result of this orcad simulation:
I constructed a basic schematic of an asynchronous 4 bit counter using JK flip-flops. We were then asked to make the counter stop after it reaches "1111" . I used a NAND gate to take in all the Q outputs and output a 0 when they are all 1. This was going to go through an AND gate along with the clock into the clock in of the least significant flip flop in order to effectively remove the clock from the circuit when this state occurs. The teacher has even explained this kind of setup to us and in theory it makes perfect sence but i dont know why this simulation is not working. In the schematic attached i have left the output of the NAND gate floating and removed the AND gate as they were not working anyway and I am still strying to figure out why the output of the NAND gate is not working properly.
Also could someone please tell me what the blue lines mean as opposed to the normal green output.
Cheers!
I constructed a basic schematic of an asynchronous 4 bit counter using JK flip-flops. We were then asked to make the counter stop after it reaches "1111" . I used a NAND gate to take in all the Q outputs and output a 0 when they are all 1. This was going to go through an AND gate along with the clock into the clock in of the least significant flip flop in order to effectively remove the clock from the circuit when this state occurs. The teacher has even explained this kind of setup to us and in theory it makes perfect sence but i dont know why this simulation is not working. In the schematic attached i have left the output of the NAND gate floating and removed the AND gate as they were not working anyway and I am still strying to figure out why the output of the NAND gate is not working properly.
Also could someone please tell me what the blue lines mean as opposed to the normal green output.
Cheers!
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