Hi.

I have some fundamental misunderstanding I am hoping you can help me with.

Attached image ckt1.png shows my test circuit.



It is a ~10:1 voltage divider (high resistances to look at a large voltage).
It is followed by a non-inverting opamp buffer.

To build the circuit, the source is an AFG set to high output impedance, 5Vpp, 2.5V offset.
For the amplifier I tried three parts: an NE5532, a TL972, and an LM6132. These are all dual chips, and the unused amp is correctly terminated.

The amplifiers are powered with +/- 5V rails.

Because the divider resistances are large, some loading is to be expected, both by the opamp input, and by the scope probe if placed at the divider. In fact, 10M probe on ~1M divider will load a 500mV signal down to 450mV.

I'm trying to come up with an explanation as to why the measurements I made were different for each chip:
1) NE5532: buffer output swings between -172mV and 324mV (delta of 496mV)
2) TL972: buffer output swings between 628mV and 1.120mV (delta of 492mV - measured at tighter 200mV/div because of larger offset)
3) LM6132: buffer output swings between 80mV and 576mV (delta of 496mV)

The output offsets are large, and unexpectedly varied from chip to chip. Does anyone know why this might be?

 

You could analise the output stage of each opamp if you know the schematics.

 

Are the grounds of your voltage source and your opamp connected together?

Bob

 

A quick check of the three datasheets, shows that Input Bias Current and Input Offset Current easily reach 100 nA.
Since the amplifier is unbalanced by 900KΩ in +Inp and 0Ω in -Inp may very easily provide 100 mV offset.
I would suggest putting 900 KΩ parallel with few pF in the feedback connection from the output to -Inp.

 

The input bias current of the '5532 is between 0.2uA and 0.8uA. This current flows through R5 and R16 - equivalent parallel resistance about 1MΩ. This will generate an offset voltage between 0.2V and 0.8V. You will get some cancellation of that if you include a 1MΩ resistor in the feedback around the opamp. Better, select an opamp with very, very low input bias and offset currents - FET input.

[Dash it - beaten to the punch]

 

Yes, grounds are tied together. Levels are all rock solid, no floating effects.

Regarding the comment on output stages - two out of three of the datasheets have functional block diagrams. I wish I could understand them enough to be able to discover what the root cause is.

Input bias current appears to be the correct answer! The feedback passthrough cap is a great suggestion too, it really cleans up the output.

In my real, more complicated circuit, the divider is unfortunately switched. It is a small divider when observing a small voltage drop, and a large divider when observing a large drop. This will make the input current matching a challenge

 

You could select a low input current opamp. You will have to look at the specs and prices. LMC6001 would be great, but very expensive. AD8659 is pretty good and a lot cheaper.

 

Thanks for your suggestions, I will explore.

 

CMOS opamps have relatively poor offset specs, but huge input impedances and very low bias currents. Back in the 90's, National or PMI introduced an opamp with bias currents down in the fA range.

ak