I am new to this subject and am having trouble understanding this topic.
Suppose I have the following circuit to control the forwarding of a MIPS
pipeline processor:
So the forwarding control will be in the EX stage because the ALU
forwarding multiplexors are found in that stage.
These are the control values for the forwarding multiplexors :
The goal here is to deal with the data hazards and to pass proper values
early from the pipeline registers to ALU rather than writing for the WB
stage to write the register file.
This is the truth table that I have for this circuit : I filled some of
the cases :
How exactly are the output signals ForwardA and ForwardB selected when EX/MEM and MEM/WB are at 1 and WBHazardRt ist at 1 ?
Suppose I have the following circuit to control the forwarding of a MIPS
pipeline processor:
So the forwarding control will be in the EX stage because the ALU
forwarding multiplexors are found in that stage.
These are the control values for the forwarding multiplexors :
The goal here is to deal with the data hazards and to pass proper values
early from the pipeline registers to ALU rather than writing for the WB
stage to write the register file.
This is the truth table that I have for this circuit : I filled some of
the cases :
How exactly are the output signals ForwardA and ForwardB selected when EX/MEM and MEM/WB are at 1 and WBHazardRt ist at 1 ?
