I am trying to understand common mode voltage a little bit fundamentally (only with electronic devices and no math).
I watched this Youtube Video to understand common mode and differential mode voltage.

When he explains the circuit and draws the waveform, the waveforms represent the voltage at the collector or the voltage at the base? (let us assume they are transistors for simplicity instead of MOSFETs) Are those sine waves taken at the base of the transistors or at their collectors?
Please tell me whether my understanding is correct :
So, in this type of circuit, we always need to bias the transistors when we need to use them as amplifiers. So, while biasing, we set the voltage at the collector with the help of the collector resistor, right? So, the voltage measured at the collector of the transistor during OFF condition of the transistor is called as the common mode voltage right?
This is Another video which I referred to understand the biasing of transistors when they need to be used as amplifiers
And this voltage is the bias voltage of the transistors which is 1.2V (Common mode voltage of LVDS) incase of LVDS driver circuit right?
Can someone tell me whether I am right or wrong? If I am wrong, please explain me the concept of common mode voltage with out math and only with the transistors and electronics. Please.

 

When he explains the circuit and draws the waveform, the waveforms represent the voltage at the collector or the voltage at the base?

Waveforms can be either at base or collector.

(let us assume they are transistors for simplicity instead of MOSFETs)

MOSFET is a transistor. You mean BJT (Bipolar Junction Transistor).

Are those sine waves taken at the base of the transistors or at their collectors?

Can be either. It looks like waveform at the base/gate.

So, in this type of circuit, we always need to bias the transistors when we need to use them as amplifiers. So, while biasing, we set the voltage at the collector with the help of the collector resistor, right?

The collector (or drain) resistor is the load. Bias voltage is usually applied at the base (or gate).

So, the voltage measured at the collector of the transistor during OFF condition of the transistor is called as the common mode voltage right?

For linear amplifiers the transistors are biased in the linear region, not OFF, not ON.

And this voltage is the bias voltage of the transistors which is 1.2V (Common mode voltage of LVDS) incase of LVDS driver circuit right?

Common mode voltage is the voltage that is seen at both input (bases/gates). It is the unwanted voltage that is common to both inputs. Since this is a differential amplifier the common mode voltage is not amplified as much as the signal. You want to reject common mode voltage in the amplifier. This rejection is known as CMRR (Common Mode Rejection Ratio). You want CMRR to be high, for example, greater than 80dB.

Common mode voltage is usually noise into the system. The goal is to amplify signal and not the noise. This is the reason systems use differential signalling, cables, and amplifiers. LVDS is Low Voltage Differential Signalling. RS-485 and USB are also examples of differential signalling.

 

Waveforms can be either at base or collector.
MOSFET is a transistor. You mean BJT (Bipolar Junction Transistor).
Can be either. It looks like waveform at the base/gate.
The collector (or drain) resistor is the load. Bias voltage is usually applied at the base (or gate).
For linear amplifiers the transistors are biased in the linear region, not OFF, not ON.
Common mode voltage is the voltage that is seen at both input (bases/gates). It is the unwanted voltage that is common to both inputs. Since this is a differential amplifier the common mode voltage is not amplified as much as the signal. You want to reject common mode voltage in the amplifier. This rejection is known as CMRR (Common Mode Rejection Ratio). You want CMRR to be high, for example, greater than 80dB.

Common mode voltage is usually noise into the system. The goal is to amplify signal and not the noise. This is the reason systems use differential signalling, cables, and amplifiers. LVDS is Low Voltage Differential Signalling. RS-485 and USB are also examples of differential signalling.

Thank you for the detailed answer. I mainly asked this question while researching about LVDS common mode voltage. Could you please explain me from where we get the common mode voltage of 1.2V in LVDS ? I wanted to understand the LVDS common mode voltage

 

In LVDS, the 1.2V input common mode voltage is merely the average voltage of the two inputs relative to system ground. The 350 mV differential input voltage (which carries the signal) is the voltage difference between the two inputs. It's no more complicated than that.

Here's a Wikipedia article that explains.

 

In LVDS, the 1.2V input common mode voltage is merely the average voltage of the two inputs relative to system ground. The 350 mV differential input voltage (which carries the signal) is the voltage difference between the two inputs. It's no more complicated than that.

Here's a Wikipedia article that explains.

I just want to know from where is the 1.2V generated. I have read the wikipedia article

 

To understand 1.2V bias, you need to look at the supply voltage. LV in LVDS stands for Low Voltage.
The supply voltage of LVDS typically ranges from 2.4V to 3.3V. You want the bias voltage to be approximately halfway between GND and Vcc. Hence about 1.2V and 1.6V. The typical specification is 1.2V.

This is the mid-point of the LVDS. All signals (whether ON or OFF) will be above or below this common mode voltage. For example, if the differential signal is 0.6V, signals ought to be 1.2 - 0.3V = 0.9V or 1.2 + 0.3V = 1.5V. This will be the voltage at the output of the LVDS driver.

Edit:

I just want to know from where is the 1.2V generated. I have read the wikipedia article

The 1.2V is not generated anywhere except at the driver, one signal will be 0.9V and the other will be 1.5V (for 600mV differential signal).
1.2V is simply the average mid-point between the pair of differential signals.

 

To understand 1.2V bias, you need to look at the supply voltage. LV in LVDS stands for Low Voltage.
The supply voltage of LVDS typically ranges from 2.4V to 3.3V. You want the bias voltage to be approximately halfway between GND and Vcc. Hence about 1.2V and 1.6V. The typical specification is 1.2V.

This is the mid-point of the LVDS. All signals (whether ON or OFF) will be above or below this common mode voltage. For example, if the differential signal is 0.6V, signals ought to be 1.2 - 0.3V = 0.9V or 1.2 + 0.3V = 1.5V. This will be the voltage at the output of the LVDS driver.

Edit:
The 1.2V is not generated anywhere except at the driver, one signal will be 0.9V and the other will be 1.5V (for 600mV differential signal).
1.2V is simply the average mid-point between the pair of differential signals.

Thank you for the answer. I am trying to understand what you are saying. But I am not able to get totally clarity. I request you to please explain your answer with the help of the circuit and the voltages during each cycle at the transistor nodes. please

 

Try Wikipedia:
https://en.wikipedia.org/wiki/Low-voltage_differential_signaling

 

Try Wikipedia:
https://en.wikipedia.org/wiki/Low-voltage_differential_signaling

Please. I tried. But it isnt helping. I request you to explain your previous answer with a circuit

 

Please. I tried. But it isnt helping. I request you to explain your previous answer with a circuit

Sorry, I cannot do better than Wikipedia.

 

In LVDS there is a lot more to it than just bias voltages on a transistor. At lot of it has to do with switching speeds and transmission line termination. You have to include the transmission line termination resistor in order to analyse the transistor bias voltages.

 

The common mode voltage is set by the device that outputs the signal that you are receiving into your LVDS inputs.

If the common mode voltage is not half of the full input range, then signal excursions high or low may get clipped.

 

Any explanation that you can provide with a circuit

 

Read this.

 

Let's take a step back for a moment.

In the original post and the attached circuit sketch from YouTube(?), what is shown is the classic (simplified) differential input stage, or the input to the diff receiver. The common mode voltage, Vcm, is defined to be the average of the two input voltages, V1 and V2, or (V1+V2)/2. That's all there is to it.

Keep in mind that LVDS is a current mode interface. That is, the driver is designed to put out a nominal current of +/-3.5 mA. When this current is applied across the destination parallel termination resistor at the receiver, nominally 100 ohms, it generates a nominal diff voltage of 350 mV.

 

Let's take a step back for a moment.

In the original post and the attached circuit sketch from YouTube(?), what is shown is the classic (simplified) differential input stage, or the input to the diff receiver. The common mode voltage, Vcm, is defined to be the average of the two input voltages, V1 and V2, or (V1+V2)/2. That's all there is to it.

Keep in mind that LVDS is a current mode interface. That is, the driver is designed to put out a nominal current of +/-3.5 mA. When this current is applied across the destination parallel termination resistor at the receiver, nominally 100 ohms, it generates a nominal diff voltage of 350 mV.

I have read everything. About LVDS Signals. But please let me know, when we measure LVDS signals on single ended probes, we measure 1.025V and 1.375V on +ve and -ve differential lines. We have a Vcm=1.2V. Why are the signals having this DC Offset? Need to understand how this DC Offset is generated and why is it needed?

 

Why are the signals having this DC Offset?

To avoid saturation delay and achieve the maximum operating speed, the signals are generated by transistors that do not saturate and are always in the active region.
(It's similar to ECL logic, and unlike TTl where the transistors saturate).
Since the circuit is powered by a single supply, biasing in the active region means operation somewhere below the supply voltage and above ground.
For LVDS the value is somewhat arbitrarily selected to be about 1.2V.

 

To avoid saturation delay and achieve the maximum operating speed, the signals are generated by transistors that do not saturate and are always in the active region.
(It's similar to ECL logic, and unlike TTl where the transistors saturate).
Since the circuit is powered by a single supply, biasing in the active region means operation somewhere below the supply voltage and above ground.
For LVDS the value is somewhat arbitrarily selected to be about 1.2V.

Thank you very much. A small request to you to just provide a circuit diagram for your explanation, please

 

To avoid saturation delay and achieve the maximum operating speed, the signals are generated by transistors that do not saturate and are always in the active region.
(It's similar to ECL logic, and unlike TTl where the transistors saturate).
Since the circuit is powered by a single supply, biasing in the active region means operation somewhere below the supply voltage and above ground.
For LVDS the value is somewhat arbitrarily selected to be about 1.2V.

And one more question, If you consider the LVDS circuit, the MOSFETs are not operating in the active region. So, how will they be biased at 1.2V when they are not in the active region. Are you saying, this is happening at the 3.5mA current source of the LVDS driver? If yes, could you provide a glimpse of the LVDS 3.5mA current source circuit and how that 1.2V is generated?

 

Can someone help