My current project is a 74 series TTL frequency counter similar to the Heathkits from the 80's using discrete logic chips and generally excluding micros and other programmable controllers. TTL over CMOS because it's aimed to be as 1980's faithful as I can at a sensible cost and practicality.

This is a very condensed overview of the issue I'm having:
This is a block diagram of my counter, the important bits anyway.
Note 1:The two waveforms in the box are reversed, the top trace should be the latch.
Note 2: The arrows pointing to it from the /1000 line should be after the /2.

Currently I'm using an RC circuit and a schmitt trigger as an edge detector to produce the latch and reset however this is highly unstable even with good caps. It seems to exibit some sort of pulse width oscillation which I can't simulate in SPICE and can't trace the interference.

As you can see the gate, count reset and the data latch are all derived from the /1000 output, this is my timebase. My issue is timing these three signals so that the reset and latch signals are timed so that the latch is definitely finished latching before the reset goes high. The 74LS75 is a bit finicky with its timings even with plenty of decoupling, it has a tendancy to unlatch if not enough time has elapsed after pulling the clock low as if there was some sort of switch bounce involved(Obviously it isn't but it has a similar sort of effect).


So there must be a tiny gap, say 100us, between latch and reset so ensure it is stable. The must also be a similar gap between the closing of the gate and the latch going high. And preferably a set pulse width unlike an RC circuit with its temp-co getting in the way.

Could someone please point me in the right direction or provide a circuit that would produce the required signals for my counter.

Thanks in advance, Sparky.



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Have you considered either a 74121 or one half of a 74123 one-shot? Using film caps will be better than ceramic caps for "slow" pulses such as 100us.

 

There's not much detail about the important part, how you are creating the pulses now. "RC" and "Schmitt" are not nearly enough detail. However (wait for it.......) a schematic IS. But while we wait for it... One way to guarantee the timing of two pulses is to derive one from the other. Timing edge > first differentiator and pulse former > that drives the latch, and its trailing edge drives the 2nd differentiator and pulse former to reset the counter. No TTL part needs 100 us to do anything. 50 ns maybe. So whatever the problem is, it isn't an internal setup time requirement of the latch.

ak

 

My current project is a 74 series TTL frequency counter similar to the Heathkits from the 80's using discrete logic chips and generally excluding micros and other programmable controllers. TTL over CMOS because it's aimed to be as 1980's faithful as I can at a sensible cost and practicality.

This is a very condensed overview of the issue I'm having:
This is a block diagram of my counter, the important bits anyway.
Note 1:The two waveforms in the box are reversed, the top trace should be the latch.
Note 2: The arrows pointing to it from the /1000 line should be after the /2.

Currently I'm using an RC circuit and a schmitt trigger as an edge detector to produce the latch and reset however this is highly unstable even with good caps. It seems to exibit some sort of pulse width oscillation which I can't simulate in SPICE and can't trace the interference.

As you can see the gate, count reset and the data latch are all derived from the /1000 output, this is my timebase. My issue is timing these three signals so that the reset and latch signals are timed so that the latch is definitely finished latching before the reset goes high. The 74LS75 is a bit finicky with its timings even with plenty of decoupling, it has a tendancy to unlatch if not enough time has elapsed after pulling the clock low as if there was some sort of switch bounce involved(Obviously it isn't but it has a similar sort of effect).


So there must be a tiny gap, say 100us, between latch and reset so ensure it is stable. The must also be a similar gap between the closing of the gate and the latch going high. And preferably a set pulse width unlike an RC circuit with its temp-co getting in the way.

Could someone please point me in the right direction or provide a circuit that would produce the required signals for my counter.

Thanks in advance, Sparky.

When/if you get this figured out, I can send you some vintage 70s/80s chips to build it. I gotta see more than this that it will get done though.

 

Currently I'm using an RC circuit and a schmitt trigger as an edge detector to produce the latch and reset however this is highly unstable even with good caps. It seems to exibit some sort of pulse width oscillation which I can't simulate in SPICE and can't trace the interference.

It should be very stable and repeatable even with cheap caps. Remember that a TTL input actually is a current *source* out to whatever is driving it, and floats high enough when not connected or connected to a high DC resistance to produce a logic 1 at its output. Because of this, it takes an unusually low value resistor (max. 470 ohms) to pull a TTL input low enough to be seen as a logic 0. And because of that, most pulse formers use a negative edge to yank the cap downward, and have a medium-value resistor (4.7 K -ish) to Vcc to pull the other end of the cap (and the gate input) high.

ak

 

I'm sorry my first post wasn't clear enough, here's the timing diagram to clarify what I'd like to do.



And here's what I'm using at the moment, So far this works, other than the reset occasionally being triggered before the latch is fully stable. Both signals ARE derived from each other.
I could probably fix it by using the remaining schmitt triggers in the chip to add some delay to the output but I feel that's a bit hacky.



You know what RichardO that might be perfect, I didn't even know such a chip existed. I must have glanced over in the list and completely missed it. I'll see if I can buy a couple from the local electronics shop next time I'm in.

Thanks for the very generous offer GopherT but I can't guarantee I'll finish building it, generally due to the cost of vintage parts. I'm still a student so I can't afford much and these projects end up being abandoned because of that.
If I get closer to finishing it, with a full schematic and all the boards I may take you up on the offer.
If you wouldn't mind, do you have a list of the chips you'd be willing to donate/sell? Especially any 74LS75s I can't find those anywhere. I bought the last of the electronics shop's stock and he can't source any more.

I'll let you if it worked when I get the chips! It seems like such an obvious solution now. I just hope the timing will be right this time.

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Your timing diagram tells the story. Since you haven't said, I have to assume you are using the 7490 as your decade counter. The 7490 counts on the negative edge and resets with a positive level. When your gate signal goes low, it drives the output of the AND gate low into the counter clock input. Depending on the logic level of the input signal, this might be an extra clock edge.

Separate from that, the 7475 is a transparent latch. Internally it is more like a multiplexer than a flipflop, but I digress. As long as the latch enable is high, the output tracks the input. Your timing diagram shows the RC node driving the latch input. This is the wrong signal polarity. You want the positive pulse from B driving the latch enable, and you want that pulse much more narrow and stable. Changing R to 1K significantly decreases the inverter's input current's effect on the actual time constant. Also, the more narrow the pulse is the less chance that the latch will change state while the enable is open. 0.01 uF and 1 K gives a gate time of 10 us, short enough to prevent any ambiguity and way longer than its 20 ns setup time.

Again, if you are using 7490's... the reset pulse is the wrong polarity. It should be positive-going and very short. Also, you have it firing off of the same positive edge as the latch pulse (delayed by two inverters). You want the reset pulse former to fire off the trailing edge of the latch pulse, not the leading edge. This way, the reset can not start until the latch gate is closed. I suggest moving one of the two inverters on the right of the reset pulse former to the left of the RC. This adds a tiny bit of delay between the latch closing and the reset starting, fixes the reset start edge, and fixes the reset polarity. If you add reference designators to every component on your drawings, this is much easier to describe.

Gate negative edge > RC > A > inv > B (latch enable positive pulse) > inv > inv > (Latch pulse trailing, negative edge, delayed 20 ns) into RC > inv > reset pulse.

ak