I’m trying to understand SPI modes properly and made below waveform to check if my thinking is correct.

In first waveform:
clock idle is LOW,
sender sets data at rising edge,
receiver reads at falling edge.

In second waveform:
clock idle is HIGH,
sender sets data at falling edge,
receiver reads at rising edge.



So till here I was only able to see 2 SPI modes. But then I got confused thinking:

can reverse also happen?

Like if clock idle is LOW, can receiver read at rising edge and sender set/change data at falling edge? And same doubt for clock idle HIGH.

If yes, then I can understand how remaining SPI modes are formed.

But what is confusing me is:

if receiver is reading on first edge, then when was data written/set? In my head it feels like write should happen first and then read.

I don't know what I’m missing

 

There are two control parameters, polarity CPOL, and phase CPHA.
Each parameter can be given one of two values, 0 or 1.
Hence, in total, there are four combinations of CPOL and CPHA.

 

The answer to your question "if receiver is reading on first edge, then when was data written/set?" is that the two ends of the line have to agree about how data is going to be sent/received. For example, if you've got a processor sending data serially to a 74HC495 shift register, then you have to match its requirements, because it's a hardware device that can't be reprogrammed. If both ends of the line can be programmed, then you've got to decide what the protocol is going to be, and make sure sander and receiver match.

 

There are two control parameters, polarity CPOL, and phase CPHA.
Each parameter can be given one of two values, 0 or 1.
Hence, in total, there are four combinations of CPOL and CPHA.

I know there are 4 combinations because CPOL and CPHA can each be 0 or 1.

But my actual doubt is.

When clock idle is LOW:

• can receiver read data at rising edge
• and sender write/change data at falling edge?

And when clock idle is HIGH:

• can receiver read data at falling edge
• and sender write/change data at rising edge?

If yes, then how does read happen before write/change on that clock cycle? That part is what is confusing me.

 

Control signals can either be level sensitive or edge sensitive.

SPI clock SCLK is edge sensitive. Hence we are only interested in what happens at the rising and falling edge of SCLK, not when SCLK is LOW or HIGH.

 

There are two control parameters, polarity CPOL, and phase CPHA.
Each parameter can be given one of two values, 0 or 1.
Hence, in total, there are four combinations of CPOL and CPHA.

In which processor are CPOL and CPHA used? I don't know if they're relevant to the original question or not.

 

In which processor are CPOL and CPHA used? I don't know if they're relevant to the original question or not.

SPI communication occurs between a controller (MCU) and a device. Every MCU I have used has CPOL and CPHA. This allows the MCU to communicate using any one of the four modes that the device uses.

 

Reference: https://en.wikipedia.org/wiki/Serial_Peripheral_Interface

 

Hence we are only interested in what happens at the rising and falling edge of SCLK, not when SCLK is LOW or HIGH.

I would not completely agree with you because the idle level of clock (LOW or HIGH) is exactly what CPOL defines, and that changes:

• which edge becomes the first edge
• and which becomes the second edge

Example:

If clock idle is LOW:

• first edge = rising
• second edge = falling

If clock idle is HIGH:

• first edge = falling
• second edge = rising

So even though data transfer occurs at edges, the LOW/HIGH idle state is still important because it determines edge interpretation

 

 

View attachment 367675
Reference: https://en.wikipedia.org/wiki/Serial_Peripheral_Interface

So from this I can understand how 4 SPI modes are formed.

This is exactly what I was thinking before, if clock idle is LOW then either read can happen at rising edge and write/change at falling edge, or write can happen at rising edge and read at falling edge. Similarly if clock idle is HIGH then either read can happen at falling edge and write/change at rising edge, or write can happen at falling edge and read at rising edge.

But what is confusing if receiver reads on the first edge, then how is it reading before write/change happens on that clock cycle?

 

So from this I can understand how 4 SPI modes are formed.

This is exactly what I was thinking before, if clock idle is LOW then either read can happen at rising edge and write/change at falling edge, or write can happen at rising edge and read at falling edge. Similarly if clock idle is HIGH then either read can happen at falling edge and write/change at rising edge, or write can happen at falling edge and read at rising edge.

But what is confusing if receiver reads on the first edge, then how is it reading before write/change happens on that clock cycle?

If the data is read on the first edge, the data is already present on the data line, even before any shifting has occurred.

 

MrChips, you are right. CPOL and CPHA are pretty universal terms, regardless of the processor that's in use.

I think it's easy enough to see how the relative timing works for any of the 4 modes, where the diagrams show when the data will change and on what clock transition the data will be stable, i.e. when the receiver has to accept it.

 

View attachment 367677

I think my confusion was happening because I was assuming the receiver reads the data bit at the first edge of the first clock cycle itself (CPHA=1).

In waveform 2 and 4 (CPHA=1), the first edge of the very first clock cycle is not used for reading/sampling. The first actual data set/change starts from the second edge of the clock, and then on the following edge the receiver reads that data bit.

So communication effectively starts half a clock cycle later, and that cleared my confusion about "how can read happen before write/set?".

 

I think my confusion was happening because I was assuming the receiver reads the data bit at the first edge of the first clock cycle itself (CPHA=1).

In waveform 2 and 4 (CPHA=1), the first edge of the very first clock cycle is not used for reading/sampling. The first actual data set/change starts from the second edge of the clock, and then on the following edge the receiver reads that data bit.

So communication effectively starts half a clock cycle later, and that cleared my confusion about "how can read happen before write/set?".

No. Communcation starts when /CS goes LOW followed by the first edge of SCLK.
When data is sampled depends on CPHA. If CPHA = 0, the first bit is sampled on the first SCLK edge.
If CPHA = 1, the first bit is sampled half a clock cycle later.

Data shifting and sampling never occur on the same edge of SCLK.

 

No. Communcation starts when /CS goes LOW followed by the first edge of SCLK.
When data is sampled depends on CPHA. If CPHA = 0, the first bit is sampled on the first SCLK edge.
If CPHA = 1, the first bit is sampled half a clock cycle later.

Data shifting and sampling never occur on the same edge of SCLK.

Thanks for your explanation. Now I completely understood all four SPI modes.