Trying to consolidate 2 NOTs, 3 AND into a single 74LS00

Thread Starter

TimothyG

Joined Dec 2, 2020
5
In part of my circuit I need to detect a 1, 0, 0, and a 1. With Σm = 9, F = ab'c'd. Great. I can send a signal that 9 has been detected using two NOT gates with 3 AND gates but am only allowed "one extra device for the detection logic." I was hoping to implement it using a single 7400, but I have hit a wall. I can't seem to implement the detection with fewer than 7 NAND gates. Is it even possible? Am I barking up the wrong tree? Please advise.
 

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Irving

Joined Jan 30, 2016
1,532
Are you sure the brief is 'a 7400' and not 'a device from the 7400-range of devices'? If the latter, you're artificially restricting your choice and there's more than one solution...
 

andrewmm

Joined Feb 25, 2011
1,473
In part of my circuit I need to detect a 1, 0, 0, and a 1. With Σm = 9, F = ab'c'd. Great. I can send a signal that 9 has been detected using two NOT gates with 3 AND gates but am only allowed "one extra device for the detection logic." I was hoping to implement it using a single 7400, but I have hit a wall. I can't seem to implement the detection with fewer than 7 NAND gates. Is it even possible? Am I barking up the wrong tree? Please advise.
What do you know about Karnaugh maps ?
https://en.wikipedia.org/wiki/Karnaugh_map
 

Thread Starter

TimothyG

Joined Dec 2, 2020
5
Are you sure the brief is 'a 7400' and not 'a device from the 7400-range of devices'? If the latter, you're artificially restricting your choice and there's more than one solution...
Oh no. It's not restricted to the 7400. In trying to restrict the NOTs and ANDs to one chip, I thought I would have to use the 7400 since a NOR chip wasn't included in the kit. I'm really only restricted by what came in the kit.

For my Digital Logic 1 Lab we have access to the following chips in our kit:
1IC 74LS00 Quad 2-Input Positive NAND Gate DIP-14
1IC 74LS04 Hex Inverter
1IC 74LS08 Quad 2-Input Positive AND Gate
1IC 74LS138 3-to-8 Line Decoder/Demultiplexer
1IC 74LS32 Quad 2-Input Positive OR Gate
1IC 74LS175 Quad D-Type Flip-Flop
1IC 74LS86 Quad 2-Input Exclusive OR Gate
1IC 74LS157 Quad 2-TO-1 Line Data Selector
1IC 74LS153 Dual 4-to-1 Data Selector/Multiplexer
1IC 74LS283 4-Bit Binary Full Add Fast Carry
1IC 74LS47 BCD-to-7-Segment Decoder Driver
1IC 74LS191 Synchronous 4 Bit Up Down Binary Counter 5 Volt

The 74LS157, 74LS175, and 74LS283 are being used in the rest of the circuit. The 191 is probably cheating cuz the rest of the circuit is a counter. :p

What do you know about Karnaugh maps ?
https://en.wikipedia.org/wiki/Karnaugh_map
I know the basics: How to make a table for up to 4 inputs, and then simplify the table by grouping. Oh! Don't cares!

I probably should have don't cares for any values after 9 actually. The entire circuit is a Mod-10 up counter, so once it reaches 9 it will reset to 0. So, any values after that should not being showing up at all...
ab/cd00011110
00
01
11XXXX
101XX
f = ad

Which can easily be implemented using a single 7400.
Does that sound right?

If you are allowed "one extra device for the detection logic" then make sure that device is a 7485.
Alas, I don't have that one.
 

Ian0

Joined Aug 7, 2020
2,235
I probably should have don't cares for any values after 9 actually. The entire circuit is a Mod-10 up counter, so once it reaches 9 it will reset to 0. So, any values after that should not being showing up at all...
If your "nine" resets the counter ,and you are not bothered about 10, 11, 12, 13, 14 and 15 then it's trivial. You should be able to spot it without a Karnaugh map.
 

dl324

Joined Mar 30, 2015
12,871
I can send a signal that 9 has been detected using two NOT gates with 3 AND gates but am only allowed "one extra device for the detection logic." I was hoping to implement it using a single 7400, but I have hit a wall. I can't seem to implement the detection with fewer than 7 NAND gates.
It can be done with one gate. Think about it...
 

MrChips

Joined Oct 2, 2009
23,535
It depends on what you are trying to do and what the rest of the circuit does.
For counting up, F = D.A will detect 9.
If you are not concerned with glitches, F = D.B will detect 10 and can be used to reset a 0-9 ripple counter.
 

Thread Starter

TimothyG

Joined Dec 2, 2020
5
SN74138 will give you inverted output.
Thank you for the reminder.

I can get detecting 9 down to two inputs
hihglight the squares you are addressing,
Sorry. Forgot to do that. I have the grouping I used to get in bold and green below.
I'll give you a clue - make it so that it would also detect 11, 13 and 15.
Isn't that what I did with f = ad? I highlighted the group I used as andrewmm pointed out. Is that it or are you referring to something else?

ab/cd​
00​
01​
11​
10​
0​
1​
11​
X​
X
X
X​
10​
1
X
X​
f = ad

It depends on what you are trying to do and what the rest of the circuit does.
For counting up, F = D.A will detect 9.
If you are not concerned with glitches, F = D.B will detect 10 and can be used to reset a 0-9 ripple counter.
Detecting the 9 is enough. I've posted an image from CircuitVerse so that you can see the rest of the diagram.

If your "nine" resets the counter ,and you are not bothered about 10, 11, 12, 13, 14 and 15 then it's trivial. You should be able to spot it without a Karnaugh map.
Do you mean the 1s in 1001?

It can be done with one gate. Think about it...
Got it.

Test_Bed.png
I was able to implement the detection logic in CircuitVerse using two NAND gates. Thanks all for your help. Now I just have to get it wired up.
 

andrewmm

Joined Feb 25, 2011
1,473
Thank you for the reminder.


Sorry. Forgot to do that. I have the grouping I used to get in bold and green below.

Isn't that what I did with f = ad? I highlighted the group I used as andrewmm pointed out. Is that it or are you referring to something else?

ab/cd​
00​
01​
11​
10​
0​
1​
11​
X​
X
X
X​
10​
1
X
X​
f = ad


Detecting the 9 is enough. I've posted an image from CircuitVerse so that you can see the rest of the diagram.


Do you mean the 1s in 1001?



Got it.

View attachment 237316
I was able to implement the detection logic in CircuitVerse using two NAND gates. Thanks all for your help. Now I just have to get it wired up.

Well done you
a perfect engineering route followed,
best of luck in the future,
 
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