In part of my circuit I need to detect a 1, 0, 0, and a 1. With Σm = 9, F = ab'c'd. Great. I can send a signal that 9 has been detected using two NOT gates with 3 AND gates but am only allowed "one extra device for the detection logic." I was hoping to implement it using a single 7400, but I have hit a wall. I can't seem to implement the detection with fewer than 7 NAND gates. Is it even possible? Am I barking up the wrong tree? Please advise.
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