# Truth table for a CMOS circuit

Discussion in 'Homework Help' started by vik87, Oct 3, 2016.

1. ### vik87 Thread Starter New Member

Oct 3, 2016
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Hi Guys, I am taking up a course on edx about the c9omputing technology. In my homework i have to make a truth table for this cmos circuit

I figured out the top half of it, but i dont know whats going on at the bottom. Are all of the four n-types in series or are the top two in series and then in parallel with the bottom two(also in series). Any help would be appreciated. Thanks

2. ### dl324 AAC Fanatic!

Mar 30, 2015
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This is homework. You're expected to show your work.

3. ### WBahn Moderator

Mar 31, 2012
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You say you figured out the top half. Well, are all the p-types in series? Why doesn't the answer to that question apply to the four n-types since the top and bottom have identical topologies?

There are only four possible combinations of input. Just go through each one and see if there is a pullup path and/or a pulldown path. Are there any combinations that have both or have neither?

4. ### vik87 Thread Starter New Member

Oct 3, 2016
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I am looking for someone to help me understand the problem not solve it for me.

5. ### WBahn Moderator

Mar 31, 2012
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The best way we can help you understand the problem is to see how YOU attempt to solve the problem. That let's us see what kind of approach you are taking, what assumptions you are making, what you are doing right, and what you are doing wrong.

6. ### vik87 Thread Starter New Member

Oct 3, 2016
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Thanks WBahn,The top will pull-up only when both the inputs are equal. Now, for input of a=1, b=1 the output will be connected to the ground and it will also be conncected to voltage but we were specicifcally told that it has to connect either one of them but not both. Am i missing something?

7. ### WBahn Moderator

Mar 31, 2012
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You are correct that, for a proper CMOS logic circuit, the output should be either pulled up or pulled down for each possible input. Not both. Not neither. If it is neither, then the output is floating for that combination. This has very real uses in logic circuits, even though it is technically not a proper CMOS circuit. But if it is both then this is almost always a design error as you are effectively shorting the supply rails and getting a large "shoot-through" current that can damage the chip and/or corrupt the behavior of other parts of the circuit depending on how stiff the rails are. It would be a very rare and specific application that would want this behavior.

8. ### vik87 Thread Starter New Member

Oct 3, 2016
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In that case what is the significance of having 4 n-types rather than two. It would essentially be the same thing

9. ### WBahn Moderator

Mar 31, 2012
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I have no idea what you are talking about because there are multiple ways to interpret what you are saying. Which two n-types are you recommending to keep? What is special about the n-types that prompts this question yet no corresponding question is prompted by the 4 p-types?

Once again -- show the truth table for the circuit. There are only four input combinations. Why won't you even attempt to produce the table?

You said, "for input of a=1, b=1 the output will be connected to the ground...."

How?

If a=1 and b=1, which transistors will be on and which will be off?

How will those transistors in those states result in the output being connected to ground?

10. ### vik87 Thread Starter New Member

Oct 3, 2016
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The truth table that i have come up with is:
A B | C
1 0 | 0
0 0 | 1
1 1 | 1
0 1 | 0
but i am not too sure about the input (1,1)

11. ### dl324 AAC Fanatic!

Mar 30, 2015
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What is it that you're not certain about?

12. ### WBahn Moderator

Mar 31, 2012
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Well, since you give absolutely no clue as to why you think that the output for 11 is 1 or why you aren't sure about it, it is pretty much impossible for me to read your mind and divine either of those.

Your truth table above implies that the output is pulled high when the inputs are the same and pulled low when they are different. What's the problem?

13. ### vik87 Thread Starter New Member

Oct 3, 2016
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I came up with that table assuming that A' = notA and B'=notB, I am not sure if that is the case

14. ### WBahn Moderator

Mar 31, 2012
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That's the normal interpretation.

So, given that interpretation, do you still have any uncertainties?

15. ### vik87 Thread Starter New Member

Oct 3, 2016
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That clarifies everything. I should have mentioned that in the beginning, sorry about that. Thanks for your help and patience.