This is a followup to an old thread. The circuit provides a 24 volt DC pulse once a minute to a clock.

I built the circuit designed by @LowQCab and find that it's not working. The circuit is reproduced below with some annotations. I get a 6 Hz signal at pin 11 of CD1, but only if I disconnect pin 15 of CD1 AND if I hover my hand over the circuit or over parts of the power cord. Without the handwaving, there is no signal. I've checked connections as best I can but can't figure out what the problem is. Any suggestions appreciated.

 

I don't understand why the reset pin is being used in the two divide by 10 4017s, perhaps someone could explain.

Seems like that would only divide by 9. <shrug>

 

I don't understand why the reset pin is being used in the two divide by 10 4017s, perhaps someone could explain.

Seems like that would only divide by 9. <shrug>

I'm wondering too.

If I ground pin 15, then I get a stable 5 or 6 Hz signal at pin 3 of the first 4017.

 

Try grounding the reset pin of both divide by 10 counters (remove the connection to pin 11)

And change the reset pin of the two divide by 6 counters to pin 6. (output 7)

CORRECTED: See below.

 

Try grounding the reset pin of both divide by 10 counters (remove the connection to pin 11)

And change the reset pin of the two divide by 6 counters to pin 6. (output 7)

Yes, will do that, thanks.

To cascade from the third counter to the fourth, do I get the output from pin 1 or pin 6? I'm reading online sources and it's not clear.

 

Leave the output of pin 1 connected to the clock of the next counter and use pin 1 as shown on the last. (driving the NMOS)

Only change the reset pin.

 

Just as a general rule you should not use the output that resets the counter as the divided output of the counter.

 

I think I made a mistake on which pin to connect the reset pin to on the count by 6 timers.

Should be pin 5 (output 6)

I need to check something to be sure.

EDIT: Yes, this is correct, it's pin 5 to pin 15 for divide by 6.

 

I think I made a mistake on which pin to connect the reset pin to on the count by 6 timers.

Should be pin 5 (output 6)

I need to check something to be sure.

EDIT: Yes, this is correct, it's pin 5 to pin 15 for divide by 6.

OK, thanks. I've got it working now. Amazing (for me). First time working with counters and some of the other components.

 

There is a "Clock Enable" pin on every 4017 counter that must be in the proper logic state. AND all of the inputs must be connected, none floating, or strange things happen.
You could also use a single binary counter and decode every count of 60 or every count of 3600. That would be simpler, One binary divider and a dual 4 input AND gates

 

There is a "Clock Enable" pin on every 4017 counter that must be in the proper logic state. AND all of the inputs must be connected, none floating, or strange things happen.

Thanks, strange things were indeed happening, but that is fixed now.

I have a question about the "Soft switching adjustment". The 47 µF capacitor on the output of the 4017 must be charging via the 1 meg resistor, right? That implies a time constant of 47 seconds... but in reality it charges almost instantly. Is there an explanation?

 

I have a question about the "Soft switching adjustment". The 47 µF capacitor on the output of the 4017 must be charging via the 1 meg resistor, right? That implies a time constant of 47 seconds... but in reality it charges almost instantly. Is there an explanation?

The 47uf cap is effectively a short circuit when voltage is first applied from pin1 of CD4.
FET2 and 3 will switch ON immediately. As the cap begins charging the voltage at the gates will slowly decrease to the level that both mosfets are completely OFF.

 

The 47uf cap is effectively a short circuit when voltage is first applied from pin1 of CD4.
FET2 and 3 will switch ON immediately. As the cap begins charging the voltage at the gates will slowly decrease to the level that both mosfets are completely OFF.

It is as you say. Pin 1 goes high and the gate voltage immediately goes to almost 5V, then declines to around 2 V after about 5 sec. Pin 1 then turns off, and with that, the gate voltage swings to -2.5v, then gradually goes to almost zero over the next 55 sec.

I'm not able to understand why it happens this way. I know I'm missing something, but it looks like a simple RC circuit to me.

 

Pin 11 (Q9) is the 10th output. The NEXT clock pulse of U1 switches itself back to pin 3 (Q0). At that same time pin 12 (carry out) would send U2 to the next Q output (whatever state it is in at that moment). Reset must be held low for the counter to count.

This is my 30 second countdown timer for a rocket launcher. I'm still in the process of building it but I expect it to work.

Pins 15 (U2 & U3 MY circuit) are held low via a 100KΩ resistor. When my launch control switch is set to manual, pins 15 are held high, disabling the count. When set to Auto, U1 is actively pulsing. The counters can count because they're powered when the master power switch is ON. Please don't get lost in all the other stuff - it's not germane to this discussion.
View attachment 360480
Pin 15 (CD1 of your schematic) is held low until a very very short moment after the last clock pulse was triggered. Q9 has gone high, thus resetting the counter. CD1 is reset to Q0. There is no carry out. At the same time U1 is reset. So I'd say "Yes, it's dividing by 9, not by 10". Pin 15 has to be held low for the counter to progress. Same would be true of CD2.

Instead of using the arrangement your scheme shows, use pin 12 (carry-out) to clock the next counter. As for CD3 & CD4, I suggest using pin 1 (CD3 Q5) as the next clock pulse to CD4. CD4 Q5 (pin 1) will charge the 47µF cap briefly. VERY briefly. Until it has taken sufficient charge pin 15 will remain low. Once the cap has charged pin 15 will go high. When 15 resets CD4, Q5 will go low again. It is uncertain there will be enough time for FET2 Gate to charge enough to switch on. FET3 may be even further delayed by the 1µF cap. I'm doubtful the escarpment mechanism will even clock. Perhaps the Soft Switching Adjustment can nullify that concern.

Where did this circuit come from? With few modifications it looks pretty good. AND I don't even know if modifications are necessary. But if it IS dividing by 9 then you'll get a clock pulse once every 1.24 minutes.

3600 / 9 = 400
400 / 9 = 44.444
44.444 / 6 = 7.407
7.407 / 6 = 1.235

If you build this and you get a clock pulse once every ONE minute, 14.1 seconds then you ARE dividing by 9 and not 10.

 

It is as you say. Pin 1 goes high and the gate voltage immediately goes to almost 5V, then declines to around 2 V after about 5 sec. Pin 1 then turns off, and with that, the gate voltage swings to -2.5v, then gradually goes to almost zero over the next 55 sec.

I'm not able to understand why it happens this way. I know I'm missing something, but it looks like a simple RC circuit to me.

View attachment 360477

Don't forget - pin 1 is tied back to pin 15. The only thing that continues to hold 15 low is the time the cap is charging. Exactly how the pot is set will affect how quickly or slowly pin 15 resets. And I'm not seeing where you're getting -2.5V from. 47 and 1 µF caps are held low via the 1 MEG Ω resistor. There should be no negative voltages. Also gates of FET2 & 3 should be held low until CD4-Q5 goes high. But you DO want a quick reset of CD4 otherwise the escarpment mechanism will get hot and possibly burn out.

My approach to resetting CD3 & 4 would be to add an additional AND gate. Pins 15 would need an input from two sources simultaneously. I'd draw that from CD1 pin 5 (Q6) and CD2 pin 5 (Q6). That way CD3 & 4 get reset in short order while having given enough time for the escarpment to have advanced the clock by 1 minute. I'm sure there's math that would suggest just how long it would take to count both counters to Q6 but I don't have the brain power to calculate that out. AND you don't want to reset too quickly, you want enough time for the escarpment to do its job. Perhaps selecting two different outputs would be better. Again, you don't want to hold the escarpment too long or it can heat up.

 

Pin 1 then turns off, and with that, the gate voltage swings to -2.5v, then gradually goes to almost zero over the next 55 sec.

When pin1 returns to ground potential the capacitor begins to discharge through the pot and 1M resistor in the opposite direction which is why the meter reads a negative voltage.

 

Pin 1 is the only thing I see that can charge the cap. While pin 1 is low there should be no charging of the capacitor. The cap is shorted through the pot and the 1M resistor to ground. Only when pin 1 goes high does the capacitor see a differential between ground and power. And when pin 1 goes high it also wants to drive pin 15 high. The limiting factor of that is the rate at which the cap charges. With all the resistance on the top side of the cap pin 15 should go high fairly quickly.

No?

 

This is a followup to an old thread. The circuit provides a 24 volt DC pulse once a minute to a clock.

I built the circuit designed by @LowQCab and find that it's not working. The circuit is reproduced below with some annotations. I get a 6 Hz signal at pin 11 of CD1, but only if I disconnect pin 15 of CD1 AND if I hover my hand over the circuit or over parts of the power cord. Without the handwaving, there is no signal. I've checked connections as best I can but can't figure out what the problem is. Any suggestions appreciated.

View attachment 360465

The 1N4004 diodes in parallel with the opto look backwards, and should be connected anti-polarity with the opto LED.

 

And when pin 1 goes high it also wants to drive pin 15 high.
No?

This was corrected back around post #8, pin15 isn't connected to pin1 but to pin5.

 

This was corrected back around post #8, pin15 isn't connected to pin1 but to pin5.

Bugs the begebers out of me when people don't read everything. Here - I'm doing the same thing. Shame on me.