Depends on your CMOS logic. If you are powering the CMOS logic with 3.3 V, then this is probably not going to work, is it?My uploaded file can serve as an inverter or nor gate right? Output state switching occurs when the input to the diodes are about 1/2 the supply volts. Low is about .1 volts out. Hi out is very close to the supply volt. These voltages should be okay for CMOS logic right?
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I just need 1 inverter gate, not the whole ICWhy not use a proper CMOS inverter gate?
The output of the inverter would go to the input of a CMOS and gate.Depends on your CMOS logic. If you are powering the CMOS logic with 3.3 V, then this is probably not going to work, is it?
What is it you are trying to achieve? Why not simply use a NOR gate from the same family as the CMOS logic you are trying to interface to?
The Creator of existence. I rather come from a female rather from a male so it matters to me.Oh, and as for your poll, the creator of what? This thread? If so, why should it matter whether or not you are female?
Thanks for sharing. However, your question was very poor, in that it assumes facts not in evidence.I rather come from a female rather from a male so it matters to me.
Can you put an option on the poll for " We don't care"The Creator of existence. I rather come from a female rather from a male so it matters to me.
Be warned that discussing religious beliefs is prohibited on AAC.The Creator of existence. I rather come from a female rather from a male so it matters to me.
No. The output starts to change state when the base voltage reaches about 0.45 V, and is completely saturated when the voltage hits about 0.6 V. Since there is no voltage divider on the input, the input transition level will be below 1.25 V.Output state switching occurs when the input to the diodes are about 1/2 the supply volts.
I can't figure out the signal frequency but I'm building a clock. I guess it would be less than one Hertz. The schematc has a two input diode or gate and I would be using a four input one.There are single-gate chips available.
AK has some valid points that you should note which I will repeat.
What is driving your inverter?
Vcc should be the same as your CMOS gates downstream.
You don't need the diodes.
You don't need R1 if driven from a logic source.
Reduce R2 to 1k.
Increase R3 to 4k7.
What is your signal frequency?
I guess I Marvel and people don't recognize thatCan you put an option on the poll for " We don't care"
Wouldn't that make the clock run slow?I can't figure out the signal frequency but I'm building a clock. I guess it would be less than one Hertz.
I Marvel at people who think they can discuss an electronic circuit while keeping the schematic a secret. The help around here is free, but it does require some respect.The schematc has ...
There are 1 gate logic families - like SMD transistors with a few extra pins.I just need 1 inverter gate, not the whole IC
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