Would like if someone could look at the attached image and tell me how I am doing in attempting to answer the question. I have filled out A and B and started OUT
You already have done a mistake. The JK FF is positively triggered (as indicated by the lack of a dot in the input of its clock). That means it will change state only when its clock goes from LOW to HIGH. As a result, the JK FF will have half the frequency in its changes than the D FF.
You have made it change state when the clock goes from HIGH to LOW too, which is wrong.
When you plot the outputs of the FFs correctly, just combine them with Din as the gates indicate and get the OUT signal.
What Roh_H says is that since we said that the JK FF is positively triggered, it will change state at a transition from LOW to HIGH. But! Since that signal comes from Q' of the D FF, that transition will happen when A signal goes from HIGH to LOW.
The correction to be done is do shift the B signal by left by one tick... and do all the calculation for the gates from the begining.