https://www.electronics-tutorials.ws/sequential/conversion-of-flip-flops.html this site explains how all flip flops are constructed.

There are other types of flip flops and perhaps the most common way of constructing real flip flops is with the use of transmission gates, so that claim that that site explains how all flip flops are constructed is more than a bit overreaching.

 

Yes,but the above time diagrams arent described for transmission gates.

 

https://www.electronics-tutorials.ws/sequential/conversion-of-flip-flops.html this site explains how all flip flops are constructed.

That article doesn't include all possible implementations of a clocked RS flip flop. This is one I designed for my logic simulator:


From the link you gave:

This isn't an edge triggered RS flip flop; it's level sensitive. If the inputs change while enable is HIGH, the outputs will changed accordingly. So it might be more appropriate to call this a latch.

 

That article doesn't include all possible implementations of a clocked RS flip flop. This is one I designed for my logic simulator:
View attachment 214385

That kind of clocked RS flip flop we have not learned so only those mentioned on that article are those which are on an exam,homework or similar.

 

What I want to say is that only flip flop JK,latch D,latch SR ff T,ff D can be the possible answers for the first picture.

 

That kind of clocked RS flip flop we have not learned so only those mentioned on that article are those which are on an exam,homework or similar.

I'm not aware of any clocked RS FF.

TI had a latch:



Motorola had two flavors of RS latches:

 

I'm not aware of any clocked RS FF.

TI had a latch:
View attachment 214387


Motorola had two flavors of RS latches:
View attachment 214388

I mean clocked SR latches not ff

 

I mean clocked SR latches not ff

Why you do not accept clocked SR latch as answer?

 

I mean clocked SR latches not ff

There is no such thing as a clocked latch.

 

There is no such thing as a clocked latch.

synch

There is no such thing as a clocked latch.

There is no such thing as a clocked latch.

http://www.play-hookey.com/digital/sequential/clocked_rs_latch.html then what is this?

 

http://www.play-hookey.com/digital/sequential/clocked_rs_latch.html then what is this?

It's a latch.

What they call a clock input would more properly be called an enable:


There's all kinds of misinformation on the internet. The key is knowing enough to know when to believe something.

 

It's a latch.

What they call a clock input would more properly be called an enable:
View attachment 214394

There's all kinds of misinformation on the internet. The key is knowing enough to know when to believe something.

The same information I have at my university books.

 

The same information I have at my university books.

People who write books make mistakes and don't necessarily know everything. I've seen a lot of latches called flip flops, but the general definition is that flip flops will only change state with a clock edge; aside for set and reset which are, AFAIK,always asynchronous.

EDIT: The material you're referencing could just be old.
From: https://www.eeweb.com/profile/max-maxfield/articles/registers-vs-latches-vs-flip-flops


We were calling what you're calling a flip flop latches at least 25 years ago. The datasheet references I posted were from the late 70's/early 80's, so latch has been in used for more than 40 years.

 

English language and US v USA,

The English ( i.e. I'm right :-> ) definition of a register is different to a latch.

( For clarity , Im using rising edge and active high, but the inverse is also available in chips )

A register is edge sensitive. The output only changes due to the rising edge of the clock input. What ever is on the D input at the point the clock rises is copied to the output.

A latch , has two states, when the gate input is low, the output of the latch does not change , no matter what the input does. When the gate input is high, the output is the same as the input, as the input waggles up and down, so does the output.

I'm afraid in the general lexicon, and I'm ashamed to say quiet a lot of the engineering docs I see for schools, especially in computer science, the latch and register name is inter changeable.

 

English language and US v USA,

The English ( i.e. I'm right :-> ) definition of a register is different to a latch.

( For clarity , Im using rising edge and active high, but the inverse is also available in chips )

A register is edge sensitive. The output only changes due to the rising edge of the clock input. What ever is on the D input at the point the clock rises is copied to the output.

A latch , has two states, when the gate input is low, the output of the latch does not change , no matter what the input does. When the gate input is high, the output is the same as the input, as the input waggles up and down, so does the output.

I'm afraid in the general lexicon, and I'm ashamed to say quiet a lot of the engineering docs I see for schools, especially in computer science, the latch and register name is inter changeable.

That gate input which you said for latch in my books is defined as a clock signal,so synchronized latch,by the way thanks for the answers I learned new things today totally different from school.I will ask the professor why they are using clocked latches.