Take a look at the datasheet for this flip-flop.
There is an example in Figure 9-1 which, if I understand correctly, sends Vcc to Q (by switching on MCU) when the button is pressed... is that right?

As you can see in the photo, let's assume these cases:

1) I do not press the button (which remains "OFF") so CLK=Vcc (logical 1) --> Q depends on D, but on D there is simply an RC that sets the delay and it's always to 0... so I do not understand how it can work...

2) I press the button (i.e. 'ON') so CLK=0 and since D=X Q=Q0... is this Q0 the previous state? Or the initial state? (that I don't know what it is..)

3) I release the button (which goes back to "OFF") so again CLK=Vcc (logical 1) -->repeat 1)








I can't understand the meaning and what happens in the step 2)
Where am I going wrong?

Thanks

 

the CLK action is happening at the moment when you press the button, literally at the transition of the signal from LOW to HIGH (or HIGH to LOW - if it has a dash above). So at that very moment you update Q and Q' depending on the input states. After that you update everything else for the next CLK.

So before the first pressing of the button, I assume D would be low. So when CLK happens with D low, Q will go low and Q' will go high.

First CLK is done, now we prepare for the next CLK, which means we transfer the current state of Q' (which was updated in the prev step) in to the current state of D. So now D is high. So on the 2nd CLK you have H on input, which means you will get H on Q and L on Q'. Q' is the input on D for the 3rd CLK, but it would be the same as on the 1st CLK - so this circuit has toggle action, on each pressing of the button the output would change from high to low or vice versa.

I am not 100% sure how you draw the states before the first CLK, but I think there should be an "assume that..... " somewhere in the task where the states should be defined before the first CLK.

 

Let's walk through what happens after power is applied:



We start off with Vcc = 0 V.

Then, Vcc is turned on and power comes up on the 74xx17 and the 74x77 quickly, but in an unknown order. Also, the initial state of the flip flop normally would be random. How long this takes is a function of the effective impedance of the Vcc supply and how much current is draw by the devices, which will determine how much is "left over" to charge up the bypass capacitors. But we can probably assume that assuming an effective impedance of 10 Ω is probably overkill, which would make the time constant on the power rails on the order of 1 µs, so the devices should be powered up in well under 10 µs.

Now consider the time constant on input 2A of the buffer, which is 20 ms. The capacitor, which is initially uncharged, will hold the input LO until it rises above about half of Vcc, at the earliest (per the data sheet), which is going to take about 0.7 time constants, or 14 ms. Call it 10 ms to be safe. This, the /CLR input of the DFF will be held LO for long after the time that it takes the DFF to power up, thus forcing the initial state of the DFF to be LO. This will make the Q output (to the MCU) LO and the /Q output HI. The /Q output is connected to an RC circuit that drives the D input. This RC circuit has a time constant of about 7 ns. So, roughly speaking, whenever the /Q output changes, the D input will follow about 5 to 10 ns later. The purpose of this delay is to ensure that the hold time requirements on the D input are satisfied. By the time the /CLR is relaxed after 10 ms, the D input is therefore solidly at a HI input and, therefore, the DFF will change state with Q going from LO to HI on the next CLK rising edge.

This brings us to the switch. The RC time constant on this is 10 ms. When the button is pressed, the capacitor is rapidly discharged taking it to near 0 V very quickly. But this doesn't affect the DFF because it is producing a falling edge on the CLK input. When the button is released, the cap starts charging and crosses the CLK rising threshold after about 5 to 10 ms. This will then cause the output of the DFF to change state.

The end result is that the circuit should power up with the signal going to the MCU at a LO level, and then it should toggle state each time the button is released.

 

Let's walk through what happens after power is applied:

View attachment 360367

We start off with Vcc = 0 V.

Then, Vcc is turned on and power comes up on the 74xx17 and the 74x77 quickly, but in an unknown order. Also, the initial state of the flip flop normally would be random. How long this takes is a function of the effective impedance of the Vcc supply and how much current is draw by the devices, which will determine how much is "left over" to charge up the bypass capacitors. But we can probably assume that assuming an effective impedance of 10 Ω is probably overkill, which would make the time constant on the power rails on the order of 1 µs, so the devices should be powered up in well under 10 µs.

Now consider the time constant on input 2A of the buffer, which is 20 ms. The capacitor, which is initially uncharged, will hold the input LO until it rises above about half of Vcc, at the earliest (per the data sheet), which is going to take about 0.7 time constants, or 14 ms. Call it 10 ms to be safe. This, the /CLR input of the DFF will be held LO for long after the time that it takes the DFF to power up, thus forcing the initial state of the DFF to be LO. This will make the Q output (to the MCU) LO and the /Q output HI. The /Q output is connected to an RC circuit that drives the D input. This RC circuit has a time constant of about 7 ns. So, roughly speaking, whenever the /Q output changes, the D input will follow about 5 to 10 ns later. The purpose of this delay is to ensure that the hold time requirements on the D input are satisfied. By the time the /CLR is relaxed after 10 ms, the D input is therefore solidly at a HI input and, therefore, the DFF will change state with Q going from LO to HI on the next CLK rising edge.

This brings us to the switch. The RC time constant on this is 10 ms. When the button is pressed, the capacitor is rapidly discharged taking it to near 0 V very quickly. But this doesn't affect the DFF because it is producing a falling edge on the CLK input. When the button is released, the cap starts charging and crosses the CLK rising threshold after about 5 to 10 ms. This will then cause the output of the DFF to change state.

The end result is that the circuit should power up with the signal going to the MCU at a LO level, and then it should toggle state each time the button is released.

I tried to make a timeline chart based on what you said, numbering each step.
I will repeat what you wrote, but with numbers.

0) We start off with Vcc = 0 V. Then, Vcc is turned on and power comes up on the 74xx17 and the 74x77 quickly, but in an unknown order. Also, the initial state of the flip flop normally would be random. How long this takes is a function of the effective impedance of the Vcc supply and how much current is draw by the devices, which will determine how much is "left over" to charge up the bypass capacitors. But we can probably assume that assuming an effective impedance of 10 Ω is probably overkill, which would make the time constant on the power rails on the order of 1 µs, so the devices should be powered up in well under 10 µs.

1) Now consider the time constant on input 2A of the buffer, which is 20 ms. The capacitor, which is initially uncharged, will hold the input LO until it rises above about half of Vcc, at the earliest (per the data sheet), which is going to take about 0.7 time constants, or 14 ms. Call it 10 ms to be safe. This, the /CLR input of the DFF will be held LO for long after the time that it takes the DFF to power up, thus forcing the initial state of the DFF to be LO

2) This will make the Q output (to the MCU) LO and the /Q output HI. The /Q output is connected to an RC circuit that drives the D input. This RC circuit has a time constant of about 7 ns. So, roughly speaking, whenever the /Q output changes, the D input will follow about 5 to 10 ns later. The purpose of this delay is to ensure that the hold time requirements on the D input are satisfied

3) By the time the /CLR is relaxed after 10 ms, the D input is therefore solidly at a HI input and, therefore, the DFF will change state with Q going from LO to HI on the next CLK rising edge




Did I draw it correctly?
For me, the easiest way to understand it is by drawing it. Obviously, the time axis is not linear.
The points where I didn't understand what was happening are marked in red.

If this part is OK, I'll move on to the switch.

 

A few things that aren't correct.

After the power-up transient transient period of a microsecond or so, the Q and /Q outputs of the DFF are always opposite of each other (except, possible -- probably really -- for a very small amount of time during state changes since they aren't going to make their transitions at exactly the same time or same rate).

The D-input always followed the /Q output, just delays by a few nanoseconds.

The DFF state is going to toggle at each rising edge of CLK.

 

A few things that aren't correct.

After the power-up transient transient period of a microsecond or so, the Q and /Q outputs of the DFF are always opposite of each other (except, possible -- probably really -- for a very small amount of time during state changes since they aren't going to make their transitions at exactly the same time or same rate).

The D-input always followed the /Q output, just delays by a few nanoseconds.

The DFF state is going to toggle at each rising edge of CLK.

Picture updated with pink waveforms.
at the right the switch pressed .. at the left is when you say "After the power-up transient transient period of a microsecond or so, the Q and /Q outputs of the DFF are always opposite of each other" .. is my interpretation correct?
Is Q HIGH or \Q? I have supposed Q .. but I don't know


Thanks

 

Look at what the /CLR input does.

Also, you have Q changing a few times before the first CLK rising edge. How is that happening?

 

Take a look at the datasheet for this flip-flop.
There is an example in Figure 9-1 which, if I understand correctly, sends Vcc to Q (by switching on MCU) when the button is pressed... is that right?

As you can see in the photo, let's assume these cases:

1) I do not press the button (which remains "OFF") so CLK=Vcc (logical 1) --> Q depends on D, but on D there is simply an RC that sets the delay and it's always to 0... so I do not understand how it can work...

2) I press the button (i.e. 'ON') so CLK=0 and since D=X Q=Q0... is this Q0 the previous state? Or the initial state? (that I don't know what it is..)

3) I release the button (which goes back to "OFF") so again CLK=Vcc (logical 1) -->repeat 1)


View attachment 360361


View attachment 360360


I can't understand the meaning and what happens in the step 2)
Where am I going wrong?

Thanks

Hi,

Who put the 330 Ohm and 22pf cap on the Q' output? Normally you don't need that. FF's are made to be able to do this without special considerations like that.
There would have to be a very good reason for that because for one thing, digital inputs that are not made for slow rising signals should not have capacitors on them unless the circuit can clearly tolerate that. It could be an indication that there is not enough power supply bypassing like a 0.1uf cap across Vcc and Ground on the IC.

This could be a special case, but there would have to be some evidence supporting the use of those two parts. Even if there was, a series resistor alone would probably solve the 'problem'. The input capacitance of the D input would serve as a small capacitance.

BTW, what logic family is being used here?

 

Hi,

Who put the 330 Ohm and 22pf cap on the Q' output? Normally you don't need that. FF's are made to be able to do this without special considerations like that.
There would have to be a very good reason for that because for one thing, digital inputs that are not made for slow rising signals should not have capacitors on them unless the circuit can clearly tolerate that. It could be an indication that there is not enough power supply bypassing like a 0.1uf cap across Vcc and Ground on the IC.

This could be a special case, but there would have to be some evidence supporting the use of those two parts. Even if there was, a series resistor alone would probably solve the 'problem'. The input capacitance of the D input would serve as a small capacitance.

BTW, what logic family is being used here?

The datasheet for the part was linked in the original post. It's the LVC family.

Also note that the circuit being discussed was taken directly from the data sheet, so the answer to who put them there is that the manufacturer, Texas Instruments, put them there.

This is what I said about that RC in my first response: "The /Q output is connected to an RC circuit that drives the D input. This RC circuit has a time constant of about 7 ns. So, roughly speaking, whenever the /Q output changes, the D input will follow about 5 to 10 ns later. The purpose of this delay is to ensure that the hold time requirements on the D input are satisfied."

The propagation delay from clock to the /Q output is quite variable and isn't much more than the minimum hold time requirement, so adding a few nanoseconds keeps it reliable.

In fact, this is what the datasheet itself says about this:

 

The datasheet for the part was linked in the original post. It's the LVC family.

Also note that the circuit being discussed was taken directly from the data sheet, so the answer to who put them there is that the manufacturer, Texas Instruments, put them there.

This is what I said about that RC in my first response: "The /Q output is connected to an RC circuit that drives the D input. This RC circuit has a time constant of about 7 ns. So, roughly speaking, whenever the /Q output changes, the D input will follow about 5 to 10 ns later. The purpose of this delay is to ensure that the hold time requirements on the D input are satisfied."

The propagation delay from clock to the /Q output is quite variable and isn't much more than the minimum hold time requirement, so adding a few nanoseconds keeps it reliable.

In fact, this is what the datasheet itself says about this:

View attachment 360501

Hi there,

Thanks for the info.

A long time ago I worked with an engineer whose original language was German. If he saw this design, he would have said:
"There is something fishing".
That's the exact wording (ha ha) because he thought that was what people say when they see something questionable. Instead of saying "fishy" he would say "fishing", so it was kind of comical. He was a good person though no problem there, and a friend.

The LVC type part partly explains this. The 330 Ohm resistor and 22pf cap explain the intended delay, and scaling up on the resistance we'd probably have to go up to maybe 1.2k if we wanted to get rid of the cap. However, since it is a very high-speed device, the 330 Ohm choice is justified and of course that means the extra cap is justified. Whether or not this actually works in every case in real life is another question though, but I don't want to have to take the time to investigate this nuance. Due to the application itself though the 1.2k would probably work ok, but also we might not need any of that due to human response times.

The fact that it is a very high-speed device brings up another question though that's not as subtle.
Why are they using a 200MHz device to debounce a push button switch?
Maybe it's just part of the exercise with no practical value?

 

Due to the application itself though the 1.2k would probably work ok, but also we might not need any of that due to human response times.

Human response times have nothing to do with it. The setup and hold time requirements are to ensure that the D input signal is stable at a single logic value during the period where the internal circuitry is responding to a rising clock edge. If the D input changes during that time, the whole question of what the Q output should become is undefined. There is also the possibility of metastability if these requirements aren't honored.

If your 1.2 kΩ value is based on the pin input capacitance, relying on that value is not a good idea. TI does not guarantee anything about that value beyond it typically having a value of 5 pF. This is also a very crude characterization because it is almost certainly a highly non-linear capacitance associated with the pad input protection circuits, such as punch-through devices.

The fact that it is a very high-speed device brings up another question though that's not as subtle.
Why are they using a 200MHz device to debounce a push button switch?
Maybe it's just part of the exercise with no practical value?

General best practices are to not mix components from different logic families, so if this family was chosen to meet the needs of the critical part of the circuit, it is best to use this family for the low-speed human interface portions, too. If you mix families, then the rather considerable burden of ensuring that the compatibility requirements across all operating conditions for your circuit are met are up to you.

 

Human response times have nothing to do with it. The setup and hold time requirements are to ensure that the D input signal is stable at a single logic value during the period where the internal circuitry is responding to a rising clock edge. If the D input changes during that time, the whole question of what the Q output should become is undefined. There is also the possibility of metastability if these requirements aren't honored.

If your 1.2 kΩ value is based on the pin input capacitance, relying on that value is not a good idea. TI does not guarantee anything about that value beyond it typically having a value of 5 pF. This is also a very crude characterization because it is almost certainly a highly non-linear capacitance associated with the pad input protection circuits, such as punch-through devices.



General best practices are to not mix components from different logic families, so if this family was chosen to meet the needs of the critical part of the circuit, it is best to use this family for the low-speed human interface portions, too. If you mix families, then the rather considerable burden of ensuring that the compatibility requirements across all operating conditions for your circuit are met are up to you.

Hi,

Well the 1.2k was just a theoretical idea that would have to be modified it needed, and the timing was not too critical.

The human response time seems to play a part in this because it looks like the D input has plenty of time to settle into one logic state before the next change on the clock input might occur. At 200MHz this would be much different I would think, and the data sheet probably assumes that, and the values may not even be right come to think of it (no worries there for now though).
The only question then is, can the MCU really require an input from a 200MHz device? This circuit is actually on the data sheet!

I'm not sure what you mean about mixing logic families. If we used say a LS version then we would use an LS version for the Schmitt trigger gates too I would think, unless we could not do that for some reason. I find it hard to believe that the MCU input would require an input from a 200MHz device.

Also, a faster rise or fall is often ok going into a slower response family as long as the other specs match well enough. Just have to watch out for ringing and stuff like that.

I just thought it was funny that a 200MHz device was being used when human response times are involved such as when pushing buttons. That sounds like a problem in itself. I guess maybe the MCU could have some fast specs of some kind.

 

Hi,

Well the 1.2k was just a theoretical idea that would have to be modified it needed, and the timing was not too critical.

The human response time seems to play a part in this because it looks like the D input has plenty of time to settle into one logic state before the next change on the clock input might occur.

It has NOTHING to do with the NEXT clock input change!

Do you understand what a hold time specification is?

The hold time is how long after the CURRENT clock input change that the input must remain at a stable logic level.

If the output of the DFF is fed back to an input, and the output changes too quickly, then in the input will change before the expiration of the hold time requirement. It has NOTHING to do with clock speed or human involvement.

 

It has NOTHING to do with the NEXT clock input change!

Do you understand what a hold time specification is?

The hold time is how long after the CURRENT clock input change that the input must remain at a stable logic level.

If the output of the DFF is fed back to an input, and the output changes too quickly, then in the input will change before the expiration of the hold time requirement. It has NOTHING to do with clock speed or human involvement.

Hello again,

Oh yes, I had forgotten about that. This is what amounts to a T (toggle) flip flop. I should have reviewed it more carefully.

I'm still a little puzzled though over why a 200MHz device is being used for a human interface device whose clock frequency is probably very low. Even a lowly 20MHz device would have been an overkill

 

Hello again,

Oh yes, I had forgotten about that. This is what amounts to a T (toggle) flip flop. I should have reviewed it more carefully.

I'm still a little puzzled though over why a 200MHz device is being used for a human interface device whose clock frequency is probably very low. Even a lowly 20MHz device would have been an overkill

So, you're saying that a system that needs logic capable of running at 200 MHz never needs to have a human interface???

 

So, you're saying that a system that needs logic capable of running at 200 MHz never needs to have a human interface???

Hi again,

Well, I think that 'needs' is a strong constraint to impose here when we can see that the input is from a human being, and the output appears to be completely tolerant of a slower rise and fall time for the input signal. Of course, the final answer would have to come from a study of the MCU input requirements, but usually they are not very stringent for rise and fall times and are probably compatible with LS TTL or similar devices.

The slower outputs of an LS family should work out better because I don't think a device like a 74LS74 needs a delay on the D input like the higher speed family does. I think the CLK to Q' propagation delay is longer than the hold time.

Now there is also the question of what component sections were left over after the main part of the design. If only 200MHz devices were left over, then we might tend to use those rather than introduce more components. In that case I guess we'd be stuck using the little delay circuit.

I guess we also have to consider the sometimes non-realistic value of homework assignments.

 

It's not that unrealistic at all. Again, the circuit is NOT from some homework assignment -- it is a reference design from the manufacturer's data sheet.

If ALL I were doing was using some logic to provide a power-on circuit to a microcontroller, then I would almost certainly use a different logic family. But that is not what that reference design is for. It is a reference design for how to implement that functionality in a situation in which you have already decided to use the LCV logic family. Designers do not like to mix and match logic families without a damn good reason -- there are all kinds of demons that live in those waters.

 

It's not that unrealistic at all. Again, the circuit is NOT from some homework assignment -- it is a reference design from the manufacturer's data sheet.

If ALL I were doing was using some logic to provide a power-on circuit to a microcontroller, then I would almost certainly use a different logic family. But that is not what that reference design is for. It is a reference design for how to implement that functionality in a situation in which you have already decided to use the LCV logic family. Designers do not like to mix and match logic families without a damn good reason -- there are all kinds of demons that live in those waters.

Hi,

It's in the homework section

There is no other reference logic family. There's only a push button switch and an MCU input. It is of course possible that it is a special type of MCU, but usually they work well with LS TTL or similar. If this had to interface with another 200MHz device, of course it would be fatal to use a slower input without maybe a Schmitt trigger gate between the two.

 

It's in the homework section

Have you read the original post? It starts with, "Take a look at the datasheet for this flip-flop."

It's not presented as a homework problem, but what the TS is asking for makes this a reasonable place to put it (and it is the TS that chose to post it in this forum, they could have put it in a couple of other forums quite reasonably).

There is no other reference logic family.

There doesn't need to be -- it's in the data sheet for a member of the LCV logic family. If the input of the MCU (which is just a placeholder in that reference design -- they could have simply used the word "logic" instead of "MCU" there) is not compatible with LCV logic, then that is on the system designer to deal with.

There's only a push button switch and an MCU input.

In that reference design, yes. That is a reference design for a specific functionality that is commonly needed when designing a system that has lots and lots and lots of other functionality. That is a recommended way to implement that one piece of the design.

It is of course possible that it is a special type of MCU, but usually they work well with LS TTL or similar. If this had to interface with another 200MHz device, of course it would be fatal to use a slower input without maybe a Schmitt trigger gate between the two.

Again, the "MCU" is just a place holder to indicate that the output of the FF is being used somewhere else -- it is leaving this functional block.

Notice that the reference design includes Schmitt trigger buffers precisely to address the issue of the slow rising edges associated with the RC delay elements associated with the power-on delay and push-button debounce.

 

Have you read the original post? It starts with, "Take a look at the datasheet for this flip-flop."

It's not presented as a homework problem, but what the TS is asking for makes this a reasonable place to put it (and it is the TS that chose to post it in this forum, they could have put it in a couple of other forums quite reasonably).



There doesn't need to be -- it's in the data sheet for a member of the LCV logic family. If the input of the MCU (which is just a placeholder in that reference design -- they could have simply used the word "logic" instead of "MCU" there) is not compatible with LCV logic, then that is on the system designer to deal with.



In that reference design, yes. That is a reference design for a specific functionality that is commonly needed when designing a system that has lots and lots and lots of other functionality. That is a recommended way to implement that one piece of the design.



Again, the "MCU" is just a place holder to indicate that the output of the FF is being used somewhere else -- it is leaving this functional block.

Notice that the reference design includes Schmitt trigger buffers precisely to address the issue of the slow rising edges associated with the RC delay elements associated with the power-on delay and push-button debounce.

Hi again,

Oh ok so you read it as being an arbitrary theoretical concept. I did not realize that the forum policy was to move outside posts INTO the homework section when they dealt with homework, but not to move posts inside the homework section OUT to other sections when they were not homework. Thus, almost everything inside the homework section I assume was actual homework unless I had other information which indicates it is not.

I don't think it's a bad idea though to talk about a simpler design considering the possible slower requirements of the output load device.
For example, someone else encounters this thread and sees that design solution and thinks they need to use a 200MHz device for an Arduino project (almost comical there).
I also find it a little interesting that the output can change that fast, almost too fast, which tells me it probably was not intended to be used as a toggle flip flop.

Also, the propagation vs setup and hold times are really close, some devices might not need the little delay circuit. It might be hard to figure out which ones do and don't though.

What else is a little interesting is that the section with the little circuit is titled, "Typical power button circuit". I'd think that would hardly be 'typical'.
Maybe we should look for a faster flip flop