Time diagrams of flip flops,latches

dl324

Joined Mar 30, 2015
13,806
That article doesn't include all possible implementations of a clocked RS flip flop. This is one I designed for my logic simulator:
clipimage.jpg

From the link you gave:
clipimage.jpg
This isn't an edge triggered RS flip flop; it's level sensitive. If the inputs change while enable is HIGH, the outputs will changed accordingly. So it might be more appropriate to call this a latch.
 

Thread Starter

avalox7

Joined Aug 9, 2020
31
What I want to say is that only flip flop JK,latch D,latch SR ff T,ff D can be the possible answers for the first picture.
 

dl324

Joined Mar 30, 2015
13,806
That kind of clocked RS flip flop we have not learned so only those mentioned on that article are those which are on an exam,homework or similar.
I'm not aware of any clocked RS FF.

TI had a latch:
clipimage.jpg


Motorola had two flavors of RS latches:
clipimage.jpg
 

dl324

Joined Mar 30, 2015
13,806
The same information I have at my university books.
People who write books make mistakes and don't necessarily know everything. I've seen a lot of latches called flip flops, but the general definition is that flip flops will only change state with a clock edge; aside for set and reset which are, AFAIK,always asynchronous.

EDIT: The material you're referencing could just be old.
From: https://www.eeweb.com/profile/max-maxfield/articles/registers-vs-latches-vs-flip-flops
1597025692920.png

We were calling what you're calling a flip flop latches at least 25 years ago. The datasheet references I posted were from the late 70's/early 80's, so latch has been in used for more than 40 years.
 
Last edited:

Deleted member 115935

Joined Dec 31, 1969
0
English language and US v USA,

The English ( i.e. I'm right :-> ) definition of a register is different to a latch.

( For clarity , Im using rising edge and active high, but the inverse is also available in chips )

A register is edge sensitive. The output only changes due to the rising edge of the clock input. What ever is on the D input at the point the clock rises is copied to the output.

A latch , has two states, when the gate input is low, the output of the latch does not change , no matter what the input does. When the gate input is high, the output is the same as the input, as the input waggles up and down, so does the output.

I'm afraid in the general lexicon, and I'm ashamed to say quiet a lot of the engineering docs I see for schools, especially in computer science, the latch and register name is inter changeable.
 

Thread Starter

avalox7

Joined Aug 9, 2020
31
English language and US v USA,

The English ( i.e. I'm right :-> ) definition of a register is different to a latch.

( For clarity , Im using rising edge and active high, but the inverse is also available in chips )

A register is edge sensitive. The output only changes due to the rising edge of the clock input. What ever is on the D input at the point the clock rises is copied to the output.

A latch , has two states, when the gate input is low, the output of the latch does not change , no matter what the input does. When the gate input is high, the output is the same as the input, as the input waggles up and down, so does the output.

I'm afraid in the general lexicon, and I'm ashamed to say quiet a lot of the engineering docs I see for schools, especially in computer science, the latch and register name is inter changeable.
That gate input which you said for latch in my books is defined as a clock signal,so synchronized latch,by the way thanks for the answers I learned new things today totally different from school.I will ask the professor why they are using clocked latches.
 
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