Three stage Asynchronous counter design

WBahn

Joined Mar 31, 2012
30,063
The way that his counter is drawn is that he is clocking the 'C' bistable on the rising positive edge of the clock pulse.
If you check the image he has posted of the C,B,A states they are all high on the first clock pulse.!
They all go HI as a RESULT of the first clock pulse!

Look at his sim results. Before the first rising edge all three FFs are in the LO state. So they WERE initialized somehow -- they are NOT in an indeterminant state!

So the counter starts out in State 0. Then on the first rising clock edge the C FF toggles from LO to HI. But since the Q output of this FF is used as the clock input of the B FF, it also sees a rising clock edge and so it, too, toggles from LO to HI. The same thing happens when the Q output of the B FF clocks the A FF. So the counter goes from State 0 to State 7, which is a count backwards. This behavior has absolutely nothing to do with reset it issues, it is a direct result of how the counter is wired.
 

WBahn

Joined Mar 31, 2012
30,063
Hi WB,
LTSpice does not initialise a counters bistable states, a Reset pulse is required.
Initialization of logic parts may or may not be a simulator responsibility. In the case of analog models, it's not the simulator that causes the initialization, but rather the model. If the FF is an analog subcircuit, then it often contains an IC (initial condition) on one of the charge-storage nodes forcing that node to start out at 0V (or, better, a differential initial condition forcing a 0 V differential between one of the charge-storage nodes and the subcircuit's power pins). Digital models are more simulator-specific and may or may not be able initialize themselves -- if not, then the simulator generally has a notion of "unknown" and initializes digital memory elements to that state. Most such digital and mixed-signal simulators have a configurable option to initialize all memory elements to either unknown or to a defined state (either all HI or all LO). I always wanted a simulator that supported the option of initializing memory elements to a random, but defined, state.
 

ericgibbs

Joined Jan 29, 2010
18,851
hi WB,
As we both know, in physical applications of logic devices, they do not automatically self initialise, on power up, to a predetermined state, it is the responsibility of the designer to ensure that initial conditions are met.
That is why I would advise the addition of a power on reset circuit, even in a simulation.
As we are advising students, I also it consider our responsibility to advise on 'good practice' in addition to just solving homework problems.


Eric
 
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ericgibbs

Joined Jan 29, 2010
18,851
hi ham,
I would suggest you redraw the counter circuit in the more conventional way as per the attached image.
It will then be in the same counting sequence as shown in the original question, your first post.
E
 

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WBahn

Joined Mar 31, 2012
30,063
hi WB,
As we both know, in physical applications of logic devices, they do not automatically self initialise, on power up, to a predetermined state, it is the responsibility of the designer to ensure that initial conditions are met.
That is why I would advise the addition of a power on reset circuit, even in a simulation.
As we are advising students, I also it consider our responsibility to advise on 'good practice' in addition to just solving homework problems.


Eric
Did I not advise him to address the reset issue (see Post #57)?

But the lack of a reset has absolutely NOTHING to do with all of the bits going from 0 to 1 on the first rising clock edge. They do that because that is how that counter is going to behave -- it is going to run backwards! Put in all the reset circuitry you want. Once you relax the reset and have all the bits reset to 0, on the next rising clock edge they are all going to go to 1. Why? Because that counter is going to run backwards!
 

ericgibbs

Joined Jan 29, 2010
18,851
But the lack of a reset has absolutely NOTHING to do with all of the bits going from 0 to 1 on the first rising clock edge. They do that because that is how that counter is going to behave -- it is going to run backwards! Put in all the reset circuitry you want. Once you relax the reset and have all the bits reset to 0, on the next rising clock edge they are all going to go to 1. Why? Because that counter is going to run backwards!
I am fully aware on how the version of the counter he has draw works.

We seem to be talking at cross purposes, I am trying to get the OP to use a more conventional counter circuit, in line with the original question information.
Again I would advise him to redraw the counter as I have suggested, showing a reset signal.

Knowing your attention to detail and correctness, I am puzzled why you are so resistant to my simple advice to the OP.?
 

Thread Starter

ham3388

Joined Jul 3, 2012
97
Hi dear eric...
I searched in the PSPice for the equivalent of the SET and RESET of your circuit but unfortunately I did not find it.
Instead I tried to remove the Pull-ups and put Digital Pulse, but the counter did not work. The graph lines became straight lines ,all of them.
123.png
 

Thread Starter

ham3388

Joined Jul 3, 2012
97
I am very much thankful to WBahn,absf,ericgibbs and RBR1317.
I was facing very difficulty to understand a problem about Asynchronous counter, they helped me a lot and ericgibbs provided me good resources and links to other websites.
thanks to all of you guys
Cheers
 
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