Three stage Asynchronous counter design

Thread Starter

ham3388

Joined Jul 3, 2012
97
Thanks Bro

Below is the logic circuits that I have made. Could you guys check them please. , if ok then I will go ahead with PSpice preparation.
20160814_232324.jpg

20160814_232401.jpg
 

RBR1317

Joined Nov 13, 2010
714
Could you explain in a defferent way?
What I often do for verification is to reconstruct the logic in a spreadsheet using the Boolean functions. Create an array of input variables and feed them into the logic function and check the output array with the truth table. You can also use this approach for verifying the operation of state machines. However, not having access to a logic simulator I don't know whether this method is simpler than building the gate logic in a simulator.
 

WBahn

Joined Mar 31, 2012
30,029
I didn't get you. Could you explain in a defferent way?
You can't expect to always have people that you can ask to check your work for you -- if you could, then the people paying YOU to solve a problem would probably simply offer to pay those people in the first place. So you need to develop the skills and practices to check your own work for correctness. Fortunately checking the validity of a solution is usually a lot simpler than coming up with the solution in the first place.

What if your original problem was to take the circuits you came up with and simply analyze how they behave? Could you do that? If so, then do that and compare the results to the behavior that was specified in the actual problem you were given.
 

Thread Starter

ham3388

Joined Jul 3, 2012
97
I think you guys misunderstood me. I meant to say to have a visual check on the diagrams only.
I'm trying to design the circuits using PSpice and I am facing difficulty since really I don't know how to use it.
If you have a useful links to PSpice tutorial please forward it to me specially if relevant to counter and logic design.
But really I'm very thankful for you guys because I am sure thank I learned something that is due to your help.
 

absf

Joined Dec 29, 2010
1,968
I've glanced through all the equations on post #42. One mistake I found is on your f(B)=A'.B + A.B'

F(B).jpg
This is supposed to be an XOR gate with inputs A and B. Not sure why there are 2 inverters and 2 AND gates before the XOR. Unless that XOR is actually an OR gate?

Allen
 

WBahn

Joined Mar 31, 2012
30,029
I've glanced through all the equations on post #42. One mistake I found is on your f(B)=A'.B + A.B'

This is supposed to be an XOR gate with inputs A and B. Not sure why there are 2 inverters and 2 AND gates before the XOR. Unless that XOR is actually an OR gate?

Allen
When I first saw it I had the same reaction, but this is actually a mistake that isn't a mistake.

The only time the use of the XOR gate (instead of an OR gate) would cause a problem is the case when both inputs to it are HI. But the nature of the logic preceding it ensures that this can never happen. The inverters guarantee that if the conditions for one AND gate to output a HI are met that the other AND gate is forced to output a LO.

It's certainly a suboptimal solution in that the circuit is both slower and larger than it needs to be, but as long as neither one of those is critical, it will work fine.

@ham3388: This is a shining example of what I am talking about. YOU need to at least be making an attempt to catch these mistakes instead of just asking other people to do it for you and accepting whatever you are told at face value. In this case you would have verified that the circuit, despite what was almost certainly a mistake on your part, actually produces the correct logic.

Again, just treat it as though your proposed solution is a new problem to be analyzed.

Given the following circuit:

B.png

What is the output as a function of the inputs {A,B,C}?

Inputs|Intermediate|Output
A B C | A' B' D E |(B)
0 0 0 | 1 1 0 0 | 0
0 0 1 | 1 1 0 0 | 0
0 1 0 | 1 0 1 0 | 1
0 1 1 | 1 0 1 0 | 1
1 0 0 | 0 1 0 1 | 1
1 0 1 | 0 1 0 1 | 1
1 1 0 | 0 0 0 0 | 0
1 1 1 | 0 0 0 0 | 0

Now simply compare that to the desired truth table. Do they match?
 

Thread Starter

ham3388

Joined Jul 3, 2012
97
Going through a tutorial I managed to design the following. F. F circiut and draw the graph.
Now I don't know how to connect the output of the gates to generate the final simulation or the counter.
How to configure the cicuit to get the counter work?

If possible, please guide me.
20160816_150315-1.jpg 20160816_152310.jpg
 

WBahn

Joined Mar 31, 2012
30,029
Don't you just want to monitor the output of your logic circuit? So just do the same thing you did to monitor the output of the counter circuit.
 

ericgibbs

Joined Jan 29, 2010
18,830
hi ham,
IF I am reading your plotted waveform correctly, you seem to have no Reset pulse to the counter/s.?
So the first clock pulse sets all 3 F/F outputs High, ie: logical '1'

The Reset pulse should Reset all 3 F/F's, '0', before you start clocking.
 

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WBahn

Joined Mar 31, 2012
30,029
hi ham,
IF I am reading your plotted waveform correctly, you seem to have no Reset pulse to the counter/s.?
So the first clock pulse sets all 3 F/F outputs High, ie: logical '1'

The Reset pulse should Reset all 3 F/F's, '0', before you start clocking.
No, the problem is that he has the counter set up to run backwards.

Think about when you want to flip an arbitrary bit in binary counter -- it isn't when the previous bit goes from a zero to a one, it's when the previous bit goes from a one to zero.
 

WBahn

Joined Mar 31, 2012
30,029
Then how to connect the reset ?
In the simulation you probably don't need it since the sim will probably initialize your flip flops to zero in order to get the sim to even converge. But in the real world you need to reset the counter because, in the real world, it will power up in an effectively random state. So what you typically do is provide a POR (power-on reset) circuit that holds the reset pin active for a short period of time after power is applied using a simple RC filter. In the simulator you can achieve the same goal by simply applying a one-time pulse to the rest pin at the beginning of the simulation.
 

ericgibbs

Joined Jan 29, 2010
18,830
The way that his counter is drawn is that he is clocking the 'C' bistable on the rising positive edge of the clock pulse.
If you check the image he has posted of the C,B,A states they are all high on the first clock pulse.!
 
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