# Three stage Asynchronous counter design

#### ham3388

Joined Jul 3, 2012
97
I can see in table 1 that only the data under Qc of the truth table are used in all the colomns A, B, C and D but by one order ahead.
But I'm not understanding the logic.
Can you give a hint.?

#### RBR1317

Joined Nov 13, 2010
714
I don't understand the comment: "must be connected to gate logic for resetting at intermediate count"

I can understand a manual reset (pushbutton) or disable (switch) prior to the start of counting clock pulses. But what is the need for a reset otherwise? At what intermediate count would the logic need to reset the count?

#### ham3388

Joined Jul 3, 2012
97
I meant to say for example if you want to reset the counter at the count 4 then we can connect the desired Flip flops outputs to logic gates like NAND gates then the output of the gates to the CLR line.

#### RBR1317

Joined Nov 13, 2010
714
But I'm not understanding the logic.
Can you give a hint.?
Q3, Q2, Q1 are logic inputs. A, B, C, D are independent logic outputs. You need to design the logic gate configuration individually for each output. There are four individual truth tables, there will be four separate Karnaugh maps. Note: some individual minterms may be reusable.

#### RBR1317

Joined Nov 13, 2010
714
...if you want to reset the counter at the count 4...
Does the problem require that the counter be reset at count 4?

#### ham3388

Joined Jul 3, 2012
97
No
I just gave an example

#### WBahn

Joined Mar 31, 2012
30,052
Does the problem require that the counter be reset at count 4?
But a reset is still needed since, otherwise, the counter will initialize in an unknown state.

#### absf

Joined Dec 29, 2010
1,968
What else does the table in post #7 tell you?

Allen

#### absf

Joined Dec 29, 2010
1,968
Let Q2=x, Q1=y and Q0=z;

Using the same table, can you make 4 equations describing A,B,C & D in terms of x,y,z?

Allen

#### ericgibbs

Joined Jan 29, 2010
18,848
hi ham,
The question asks for a PSpice sim, using 'D' type bi-stables [ flip/flops], NOT J/K types.

The attached image is for LTSpice, it should be enough to enable you to create your PSpice.

Regarding the 'D' logic output, note the state of 'q2' during the 0 thru 7 count [repeating sequence].

Draw up and post your PSpice version for us to check out
E

http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/

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#### ham3388

Joined Jul 3, 2012
97
Thanks again guys for guiding me.
Eric if you agree and if its not really necessary at this stages , we leave the PSpice simulation for later because I need some time to get some tutorial about using it.
How to make 4 equations to describe A,B,C and D in terms of Q1,Q2 and Q3 as was asked by Allen.
Can any one make only one just as an example?

#### ham3388

Joined Jul 3, 2012
97
One thing that I realised is that all the inputs to A, B and C are taken from Qc
with little adjustment. And for D all the exact outputs are taken. But still I'm not able to find the logic.

#### ham3388

Joined Jul 3, 2012
97
Look below I have attached the truth tabe of 4 stages counter, 4 bit.
Beside I put the denary numbers.
Table 1 Contin the benary numbers
0, 1, 3, 7, 15, 14, 12 and 8.
How from a 3 stage counter we can get the numbers 15, 14, 12 and 8.
I'm not understanding this?

#### WBahn

Joined Mar 31, 2012
30,052
I think you might be losing sight of the forest for the trees, or more accurately, are unable to focus on a tree because it is in a forest.

So try this problem (which is not directly related to your actual problem, but will hopefully help you see the approach that you need to take):

Design a logic circuit that outputs the implements the following truth table, where {A, B, C} are the inputs and Y is the output:

Code:
A B C | Y
------+---
0 0 0 | 1
0 0 1 | 0
0 1 0 | 1
0 1 1 | 1
1 0 0 | 0
1 0 1 | 1
1 1 0 | 0
1 1 1 | 0

#### ham3388

Joined Jul 3, 2012
97
I think I have understood up to some extent what you people are trying to say.
I believe that I need to make 4 similar ciciuts for A, B, C and D right ?

#### absf

Joined Dec 29, 2010
1,968
Yes, you finally got it.

#### RBR1317

Joined Nov 13, 2010
714
FYI- My experience is that using index numbers helps cut down on transcription errors. You seem to have the correct logic expression, but an incorrectly labeled gate implementation.

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#### ham3388

Joined Jul 3, 2012
97
Could you show me the corrected one please to understand my mistake?

#### WBahn

Joined Mar 31, 2012
30,052
Could you show me the corrected one please to understand my mistake?
Your gate implementation is correct, but there is an incorrect label on the middle signal -- it is labeled B·A but should be B·A'. Minor error, just a typo.

#### WBahn

Joined Mar 31, 2012
30,052
I think I have understood up to some extent what you people are trying to say.