Q3, Q2, Q1 are logic inputs. A, B, C, D are independent logic outputs. You need to design the logic gate configuration individually for each output. There are four individual truth tables, there will be four separate Karnaugh maps. Note: some individual minterms may be reusable.But I'm not understanding the logic.
Can you give a hint.?
Does the problem require that the counter be reset at count 4?...if you want to reset the counter at the count 4...
But a reset is still needed since, otherwise, the counter will initialize in an unknown state.Does the problem require that the counter be reset at count 4?
A B C | Y
------+---
0 0 0 | 1
0 0 1 | 0
0 1 0 | 1
0 1 1 | 1
1 0 0 | 0
1 0 1 | 1
1 1 0 | 0
1 1 1 | 0
Your gate implementation is correct, but there is an incorrect label on the middle signal -- it is labeled B·A but should be B·A'. Minor error, just a typo.Could you show me the corrected one please to understand my mistake?
Yes, that is correct.I think I have understood up to some extent what you people are trying to say.
I made the following circuit based on your request.
I believe that I need to make 4 similar ciciuts for A, B, C and D right ?
by Duane Benson
by Jake Hertz
by Jake Hertz
by Duane Benson