I'm looking for some assistance in designing a three stage amplifier. I plan to use the following setup:

Input Stage:
-High input impedance
-CS JFET 2N3819

Gain Stage:
-High Gain
-CE BJT 2N3904 (Beta = 216)

Buffer Stage:
-Low output impedance
-CC BJT 2N3904 (Beta = 196)

The requirements I need to meet are as follows:

1. Input impedance >= 200 kOhm
2. Output impedance <= 200 Ohm
3. AC voltage gain >= 300
4. Low frequency -3 dB point <= 50 Hz
5. High frequency -3 dB point >= 100 kHz
6. Output voltage swing >= 6 Vpp without distortion

The load resistor must be 1 kOhm and the DC power supply may not exceed 20 V.

I have attached the circuit design layout, but I'm not 100% confident that it's correct (particularly where stage one connects to stage two). Once I get that straight, I'm just looking for some help in how to calculate all of the component values to meet my design goals.

 

Looks ok so far.
You can eliminate C12 and RL1.

 

I removed the two specified components and attempted to calculate component values. However, I'm not getting the desired results. I've attached two curve traces of my 2N3904 BJTs with my Q points selected. My Q point voltages from the simulation all seem to be within a reasonable difference from what I've calculated. (All the probe boxes are in order from left to right, probe 1 to probe 9)

Q1 Calculations:
VRC = 300/38.9 = 7.71 ≈ 8 V
VCE = VRC + 1 = 9 V
VC = VE + VCE = 11.35 V
VCC - VRC = 12 V
VB = 3.05 V
VE = 2.35

One part that confuses me is, I thought the CS JFET typically only has a gain of 5-10. In this simulation, it's 4.02/.0292 = 138.

I'm also not sure how to set the input and output impedance.

I also could use some help in choosing the correct capacitor values.

I think I may need to begin calculating from stage 3 and working back but I'm not sure where to start. Any help with calculating my component values to meet the design requirements would be greatly appreciated.

 

Focus on one stage at a time.

For a gain of 300, spread the gain across the first and second stage since there is no voltage gain on the third stage.

Signal coupling capacitors C1 - C4 will determine the low frequency roll-off.
Leave these for now. You can adjust these later.

CS and CE1 are more critical since they will affect the AC gain and low frequency roll-off as well. With both of these set to 100μF you will have too much gain and no negative feedback. Reduce these to about 10μF and plot the voltage gain and frequency response of each stage.

Basically, the input impedance will be governed by the input resistance at the gate of the FET. The output impedance will be governed by the emitter resistance RE2.

 

I'm a bit concerned by the specs. What does it mean "without distortion"? Is a distortion of 1% "without distortion"? If a distortion of 0.00000001% "without distortion"?

Also, keep an eye on the power dissipation in the output stage. In order to achieve "without distortion" you need the current sent to the load to be a small fraction of the DC current in the transistor. With a 20V supply and not collector resistor, you might push the transistor too far.

Also, where did such exact beta values come from?

 

Thank you for the tips.

WBahn:
We use a loose definition of distortion. Typically, when the wave begins to round, we consider it distorted.

The Beta values are from the Curve Tracer plots that have been attached. I have two 2N3904 BJTs that I used to obtain the plots. (I will be using these two BJTs to construct the circuit once I have good simulation values)

 

So you are going to make a design that is specific to two particular transistors?

Does this really seem like a reasonable approach to designing a circuit?

If one of them gets damaged are you going to have to go back and characterize a new transistor and then retweak your component values for that new transistor?

Also, did your curve tracer give you plots that applied to the actual temperature that the transistors will be at?

 

Yes, I am designing for two specific transistors. I'm not sure what other option you would suggest other than to design the circuit to perform based on the specific transistors that will be used.

If a transistor becomes damaged, then yes, I suppose I am expected to go back and adjust the circuit accordingly (as unreasonable as it may seem).

As a student, I do not have the experience to foresee these possible complications. As far as I know, the curve tracer does not include the effect of temperature. Perhaps it is irrelevant here since I'm only working in a lab environment.

If you have any better suggestions s to how the circuit should be designed, please share your thoughts.

 

Focus on one stage at a time.

For a gain of 300, spread the gain across the first and second stage since there is no voltage gain on the third stage.

Signal coupling capacitors C1 - C4 will determine the low frequency roll-off.
Leave these for now. You can adjust these later.

CS and CE1 are more critical since they will affect the AC gain and low frequency roll-off as well. With both of these set to 100μF you will have too much gain and no negative feedback. Reduce these to about 10μF and plot the voltage gain and frequency response of each stage.

Basically, the input impedance will be governed by the input resistance at the gate of the FET. The output impedance will be governed by the emitter resistance RE2.

I've adjusted both CS and CE1 as advised and simulated the circuit again. I also attempted to plot the Voltage Gain vs Frequency of each stage but I'm not sure if I used the correct probes.

 

Yes, I am designing for two specific transistors. I'm not sure what other option you would suggest other than to design the circuit to perform based on the specific transistors that will be used.

Imagine if this were how circuits were designed in the "real world". Every transistor radio has a number of transistors in it (and more complex circuits have lots and lots of transistors). These radios are produced by the tens of thousands (if not more). Can you even imagine how much each one would cost if each radio had to be redesigned for the specific transistors that go into that radio?

That should be screaming out to you that there must be a better way.

Instead, your design should be based on either "typical" or "worst case" parameters. If you use "typical" parameters in the design, then you need to include enough margin so that it still meets spec under "worst case", (or at least that some acceptably large fraction of the units will meet spec).

A major part of accomplishing this is using circuit designs that are largely insensitive to transistor beta and that work "better" for higher actual betas. You then design using minimum beta values.

If a transistor becomes damaged, then yes, I suppose I am expected to go back and adjust the circuit accordingly (as unreasonable as it may seem).

It's extremely unreasonable. I have never designed a circuit for a specific transistor in my life. Now, I have no doubt that there are lunatic fringe projects that end up requiring such an approach. For such situations the approach generally taken is to design around a narrow tolerance on whatever component parameters are critical and then sort the actual components against those parameters and use only those that are within the narrow tolerance. Such an approach is extremely time consuming and expensive, however, so you only do that if you have no other choice.

As a student, I do not have the experience to foresee these possible complications. As far as I know, the curve tracer does not include the effect of temperature. Perhaps it is irrelevant here since I'm only working in a lab environment.

It's not the temperature of the room that counts, it is the temperature of the transistor junctions that matters. At the quiscent powers that you are going to have to operate at to meet your "without distortion" goals, the junction is probably going to be operating at 100°C or more. In general, beta increases with temperature and you may see something like an increase of nearly a factor of two compared to what you saw in the curve tracer.