Hi,

I am working on a current steering DAC circuit. I am done with schematics and layout portion of the project. Now I have to characterize its performance. I want to know the way to test it for INL and DNL through simulation. I already tested for its functionality with an Ideal ADC. I also need to know how do I test for its settling time through simulation.

I am using free tool LTSpice for all my simulations. Please, if any one can throw some light on testing techniques , it will be helpful.

regards
SG

 

Why don't you just make a model of an ideal DAC and subtract its output from your DAC's output?

 

thanks, but I was looking for some information on testing a real DAC chip.

 

thanks, but I was looking for some information on testing a real DAC chip.

That's not what you said.
Many years ago I tested a DAC by driving it with a binary counter, generating a very linear ramp with a current source and capacitor, or an integrator, and then subtracting the ramp from the DAC output.
Generating a linear ramp is not a trivial task. You must pay attention to things like capacitor dielectric absorption, current source impedance, etc.

 

Thanks for the reply, I had one more question please see my latest post

http://forum.allaboutcircuits.com/showthread.php?t=17454

 

To test for INL and DNL I would do the following ---

1. Measure the -FS voltage, mid-point voltage and the +FS voltage
and calculate INL

2. For DNL I would calculate the LSB size at all of the major carries.
For example an 8-bit DAC would have 8 major carries ---

0000 0000 to 0000 0001,
0000 0001 to 0000 0010,
0000 0011 to 0000 0100
.
.
0111 1111 to 1000 0000

(* jcl *)