....................I tried the NAND version and I'm not getting the same results? I get a high output during the gate time instead of a low?

@crutschow

Yea, you have to be careful about the information you get from forums now days.

(you are not using NAND gates,)

 

Honestly I'm not sure how close they'll need to be. The high frequency will be between 8kHz-20kHz .

A 20 kHz symmetrical square wave has a 25 microsecond up pulse width. 25 nanoseconds is 1/10th of 1%. Does whatever this thing is driving have that kind of time-domain resolution? At some point it doesn't matter. Even super-speedy digital electronics have propagation delays.

ak

 

I admit I have not stepped through every state, but I think Wally's circuit is closer than Les's. Still, I'm not sure you can cover every input combination with just one ff. If the overall net effect is A2 gating A1 on and off but with an integral-cycle restriction, then the gate signal, which is a modified A2 signal, goes true on the first A1 positive edge after an A2 positive edge, and goes false on the first A1 negative edge after an A2 negative edge. No matter how many inverters and gates you use, I don't see how to synchronize to two edges with one clock input. And I don't think either output gate state can be achieved with gating alone.

For each of the output gate states I see it as A2 going to a ff set or reset input to hold the output in a defined state, A1 going to the clock (inverted for the turn-off ff), and the D input connected for the other output state.

ak

 

I admit I have not stepped through every state, but I think Wally's circuit is closer than Les's. Still, I'm not sure you can cover every input combination with just one ff. If the overall net effect is A2 gating A1 on and off but with an integral-cycle restriction, then the gate signal, which is a modified A2 signal, goes true on the first A1 positive edge after an A2 positive edge, and goes false on the first A1 negative edge after an A2 negative edge. No matter how many inverters and gates you use, I don't see how to synchronize to two edges with one clock input. And I don't think either output gate state can be achieved with gating alone.

For each of the output gate states I see it as A2 going to a ff set or reset input to hold the output in a defined state, A1 going to the clock (inverted for the turn-off ff), and the D input connected for the other output state.

ak

I think you can look at it that they are using the FF to generate one edge and logic to generate the other.

Since the falling edge of the output always occurs with the falling edge of A1 and since the output is always LO when A1 is LO, A1 can be AND'ed with something else to directly produce the falling output edge of the output. Now we just need to produce the rising edge only at rising edges of A1 that occur when A2 is HI (without messing up the falling edge logic). We can do this by enabling the output on the first falling edge of A1 after A2 goes HI and disabling it on the first falling edge after A2 goes back LO.

 

Here are both schematics. Take your pick. (I think crutscow won.)

The second one won't work since it is forcing the output LO immediately upon a falling edge of A2. Why was the second AND gate added?

 

The second one won't work since it is forcing the output LO immediately upon a falling edge of A2. Why was the second AND gate added?

Yes, the second AND gate will allow truncation of A1 by A2, which is not wanted.

 

It is not your specific example but here is an application using a 74120 pulse synchronizer designed to do exactly what you want. It assures all pulses are of full length. A data sheet is included below. The 74120 has two modes of operation, single pulse or pulse string (your need).
I don't think you will find them at Digikey or Mouser but they are still available.
The data sheet probably has an internals drawing you could modify to your needs also.

Not homework, right?

 

It is not your specific example but here is an application using a 74120 pulse synchronizer designed to do exactly what you want. It assures all pulses are of full length. A data sheet is included below. The 74120 has two modes of operation, single pulse or pulse string (your need).
I don't think you will find them at Digikey or Mouser but they are still available.
The data sheet probably has an internals drawing you could modify to your needs also.

Not homework, right?

Taking the inerds of a 74120 ($9.00 if you can find one) and breaking it down to meet the specific needs of this thread I get this.
Not simple, but it works and assures all output pulses are of full length. At least in theory. I didn't do a simulation on it.

 

I walked through both circuits given and neither works. Both miss an A1 pulse straddling the rising edge of an A2 pulse. @Lestraveled's circuit handles A1 straddle on the falling edge of A2. Unfortunately, I haven't been able to come up with something that's much better than an AND of the two signals. Though, like the first solution, it catches the easy trailing straddle case.

First solution with the expected waveform:


Second solution from @crutschow (using the simulation schematic):


My solution (another 3 chip partial solution):

 

I admit I have not stepped through every state, but I think Wally's circuit is closer than Les's. Still, I'm not sure you can cover every input combination with just one ff. If the overall net effect is A2 gating A1 on and off but with an integral-cycle restriction, then the gate signal, which is a modified A2 signal, goes true on the first A1 positive edge after an A2 positive edge, and goes false on the first A1 negative edge after an A2 negative edge. No matter how many inverters and gates you use, I don't see how to synchronize to two edges with one clock input. And I don't think either output gate state can be achieved with gating alone.

For each of the output gate states I see it as A2 going to a ff set or reset input to hold the output in a defined state, A1 going to the clock (inverted for the turn-off ff), and the D input connected for the other output state.

I don't understand your reservations about my 1 FF circuit.
The flip-flop only changes state to Q1 high on the falling edge of the first A1 pulse after A2 goes high or low.
Q1 high allows the AND gate at the FF output to allow A1 signals to pass.
Since the FF changes on A1's falling edge, the AND gate allows integral A1 pulses through without any truncation.
Do you see a flaw in that?

 

Well obviously you cannot output the first A1 pulse if you don´t know in advance whether A2 will come, so you can either choose to ignore the first pulse or output it partially.

 

I walked through both circuits given and neither works. Both miss an A1 pulse straddling the rising edge of an A2 pulse. @Lestraveled's circuit handles A1 straddle on the falling edge of A2. Unfortunately, I haven't been able to come up with something that's much better than an AND of the two signals. Though, like the first solution, it catches the easy trailing straddle case.

One of the TS requirements was no partial pulses. So, my circuit was correct to ignore the first pulse.

 

Well obviously you cannot output the first A1 pulse if you don´t know in advance whether A2 will come, so you can either choose to ignore the first pulse or output it partially.

I'll admit that it won't be a simple solution. If this is some sort of demodulator and A1 can vary it's frequency during an A2 pulse, it's even more complex.

 

One of the TS requirements was no partial pulses. So, my circuit was correct to ignore the first pulse.

This is what the OP said:

I need the longer frequency to gate the shorter one but in a way that does not change the pulse length of any of the shorter pulses.

It's not clear to me that no pulse is better than a truncated one.

 

...................It's not clear to me that no pulse is better than a truncated one.

With two variable signal generators, even if they were locked to the same reference, missing or truncated pulses is what you will get, it is unavoidable. The TS made the call.

 

I walked through both circuits given and neither works. Both miss an A1 pulse straddling the rising edge of an A2 pulse. @Lestraveled's circuit handles A1 straddle on the falling edge of A2. Unfortunately, I haven't been able to come up with something that's much better than an AND of the two signals. Though, like the first solution, it catches the easy trailing straddle case.
........................
Second solution from @crutschow (using the simulation schematic):
View attachment 99716
..........................

Your shown operation of the FF is incorrect.
The FF Q output changes state on the falling edge of A1 for both high and low FF transitions, not immediately when A2 (the D input) goes low (as you show).
Thus there's no truncation of the A1 pulses at either the start or the end of A2 going high.

 

Just for grins , here's my circuit modified to always include the first A1 pulse after A2 goes high.
The difference is that the FF is clocked on the leading edge of A1 when A2 goes high, and then the XOR inverts the CLK so that the FF clocks on the trailing edge of A1 when A2 goes low.

One disadvantage of this approach is that the first pulse is shortened by the combined propagation delay of the XOR gate, the FF and the AND gate.
I don't think that's a real problem at the OP's operating frequencies but if it is, faster logic family chips could be used to minimize the shortening (likely to a few tens of ns with fast logic such as the 74AHCxx family).
Also it requires 3 chips instead of 2.

 

Your shown operation of the FF is incorrect.
The FF Q output changes state on the falling edge of A1 for both high and low FF transitions, not immediately when A2 (the D input) goes low (as you show).
Thus there's no truncation of the A1 pulses at either the start or the end of A2 going high.

Not following what you're describing... I clocked the flip flop on the rising edges of A1# as shown in your schematic.

 

Not following what you're describing... I clocked the flip flop on the rising edges of A1# as shown in your schematic.
View attachment 99735

That doesn't jib with your timing diagram which shows the FF Q output going low as soon as the D input goes low.

 

That doesn't jib with your timing diagram which shows the FF Q output going low as soon as the D input goes low.

It was a simulation problem. I'll add a corrected waveform diagram and leave the original so the thread still makes sense.