Just for grins , here's my circuit modified to always include the first A1 pulse after A2 goes high.

I thought that was an initial requirement.
I think using both halves of the 4013 lets the circuit be done with only two physical packages, but the XOR is a very cool move.

ak

 

Never one to let well enough along and, following Albert E's dictum, I modified Lestraveled's circuit, replacing the FF used as a latch with a NOR latch, and also using NOR gates for the other logic, as shown below.
That reduced the chip requirement to one device type with only 1¾ packages, and it gates all the short pulses within A2's window with no pulse truncation or glitches.
I imagine it could also be done with all NAND gates, if desired.

All in all, this would appear to likely be the simplest circuit to do the task.

The old saying is that, at some point, you need to shoot the engineers and say the job is done.
Perhaps that point has been reached.

 

@crutschow
Yes Yes, we are all extremely brilliant. Please let it end.

 

As best I can determine from the image, the edges of A1 and A2 are always perfectly aligned. This does not simulate the four possible input conditions when A2 transitions in the middle of an A1 up or down period.

ak

 

As best I can determine from the image, the edges of A1 and A2 are always perfectly aligned. This does not simulate the four possible input conditions when A2 transitions in the middle of an A1 up or down period.

This better?

 

This better?

The last A2 pulse isn't capturing the A1 straddle on the leading edge of A2.

Which of your circuits are being used for this case?

 

The last A2 pulse isn't capturing the A1 straddle on the leading edge of A2.

Which of your circuits are being used for this case?

How could it? That would shave the pulse.
It's designed to capture only complete A1 pulses that occur after A2 goes high.

The circuit is from my post #102.

 

How could it? That would shave the pulse.

Based on @Lestraveled's initial response, I was under the impression that it could be done; but I haven't been able to think of anything...

The OP seems to have vacated this thread so his actual requirements are still vague. If there is a solution, I'd like to have it for future reference...

 

This better?

Nailed it.

ak

 

Based on @Lestraveled's initial response, I was under the impression that it could be done; but I haven't been able to think of anything...

The OP seems to have vacated this thread so his actual requirements are still vague. If there is a solution, I'd like to have it for future reference...

See post #30.

 

See post #30.

Missed that...

Any ideas how to catch a full (minus propagation delays) pulse straddling the leading edge of A2?

 

Missed that...

Any ideas how to catch a full (minus propagation delays) pulse straddling the leading edge of A2?

You would first need two delay lines that were longer than the lowest A1 period (>125 uS)

 

......................
Any ideas how to catch a full (minus propagation delays) pulse straddling the leading edge of A2?

You're asking to go back in time to anticipate a pulse, so unless the Flux Capacitor is fully charged in your Delorean, that's not possible.

If you use a delay line as Lestraveled suggested, then the output pulses are not real time, of course.

 

............If you use a delay line as Lestraveled suggested, then the output pulses are not real time, of course.

What is real time? Real time is what you make it to be. You as the system designer can set your time reference to any time you want. With that being said, it is time for ice cold beer number 2.

 

It's a quarter to friggin' 4! You retired guys have it made.

 

Yup, you forgot to add, "on a Monday".

 

What is real time?
..................

To me "real time" is the gated pulse in is the same gated pulse out (neglecting propagation delays).

 

To me "real time" is the gated pulse in is the same gated pulse out (neglecting propagation delays).

If you delay both A1 and A2 in time (call it "late time"), then you have the original time (early time) to make your gating decisions that will affect the "late time" waveforms. It is the same as taking the video of a horse race and delaying it to the public. You know the winner of the race before the rest of the world.

 

In raster-scan video, such as our beloved NTSC, simple processing of vertical-rate information such as image enhancement required a single-line video delay so the process decider had the instantaneous video of two points, one immediately above the other. This delayed the camera system output 1 horizontal line with respect to station sync, so sync to the camera chain was advanced 1 line to zero-time the output. The video delay lines were acoustic because digital video hadn't been invented yet.

ak

 

Based on @Lestraveled's initial response, I was under the impression that it could be done; but I haven't been able to think of anything...

The OP seems to have vacated this thread so his actual requirements are still vague. If there is a solution, I'd like to have it for future reference...

The circuit lestraveled initially posted using the D flip flop is what I am using and it works exactly as I needed it to. Thanks again!