I'm designing a comparator for a reset MC which has a specific clock and i want to synchronize the output of the comparator so that it goes Hi/Lo with the rising edge of clock and not earlier, what would be the easiest way to realize that?

 

With a 'D' flip flop. The comparator output connects to D input, clock connects to clock, Q connects to MC.

 

Regards, Dana.

 

Regards, Dana.

Why two D types?

 

Explanation here -

https://web.stanford.edu/class/ee183/handouts/synchronization_pres.pdf


Regards, Dana.

 

With a 'D' flip flop. The comparator output connects to D input, clock connects to clock, Q connects to MC.

what should the Q' connected to? should i leave it floating?

 

what should the Q' connected to? should i leave it floating?

The MC reset pin - this is your reset signal.

 

The MC reset pin - this is your reset signal.

Yea i understand that's the Q but the FF has also the negation on the output that's what i was asking about.

 

Yea i understand that's the Q but the FF has also the negation on the output that's what i was asking about.

Right - the Q(bar) pin is left unconnected.

 

I have designed it as the following circuit but that's what i get at the output! can anyone explain why does it look like that it's somehow affected with the clock?