Switching Transistor Perils continued....

Thread Starter

dr.evil

Joined Aug 18, 2010
80
Gent,

I took all the advise I got from my previous thread and incorporated them into my circuit, but I still can't get some clean switching, this is my circuit du jour, including calculated DC Bias (credit goes to partsim.com):
Screenshot from 2017-11-28 19-24-10.png
Datasheet for NSS40300MZ4
And this is the transient analysis of PULSE, where ORANGE is left side of R4, and RED is base of Q2, and BLUE is collector of Q2:
Screenshot from 2017-11-28 19-27-08.png And this is the reality, RED is base of Q2, and BLUE is collector of Q2 (only got a two channel sillyscope). 100mV/div and 500ns/div. Both are AC measurements
Screenshot from 2017-11-28 19-36-56.png
And this is part of reality too, RED is is left side of R4, 4V/div and 500ns/div (DC measurement):
Screenshot from 2017-11-28 19-54-58.png

I don't get it, why wont Q2 switch off properly? and why is the pulse distorted?
 

Papabravo

Joined Feb 24, 2006
12,774
Possibly an impertinent question, but did you actually define WTF you are trying to do? I must have missed if you did.
Q2 can only be off if Q1 is off, and R3/R4 can pull the base up to V2 (10.5V)
 

Thread Starter

dr.evil

Joined Aug 18, 2010
80
In your previous post you stated So why not just duplicate that circuit? :confused:
There were other issues, I need something that works with a wider frequency spectrum, so I scrapped it feeling confident that I would be able to replicate the behavior starting from scratch.
 

Thread Starter

dr.evil

Joined Aug 18, 2010
80
Possibly an impertinent question, but did you actually define WTF you are trying to do? I must have missed if you did.
Q2 can only be off if Q1 is off, and R3/R4 can pull the base up to V2 (10.5V)
Not an impertinent question; I'm trying to put as much current through R5 every time V1 goes high, simple as that.

Q2 can only be off if Q1 is off, and R3/R4 can pull the base up to V2 (10.5V)
I believe R3/R4 does exactly that, this is the scopeshot of R3/R4:
Screenshot from 2017-11-28 19-54-58.png
 

Thread Starter

dr.evil

Joined Aug 18, 2010
80
Q2 can only be off if Q1 is off, and R3/R4 can pull the base up to V2 (10.5V)
Well, after further debugging you may be right after all, please correct me if I'm wrong.

I ran a transient analysis with period 100uS (vs. 1uS previously) and maintained the pulse (50ns rise, 50ns width, 50ns fall), and this is the sim result:
where ORANGE is left side of R4, and RED is base of Q2, and BLUE is collector of Q2:
Screenshot from 2017-11-29 11-41-23.png

It really does seem that R3/R4 can't pull up the base of Q2, do you agree? And how can I rectify that?
 

Thread Starter

dr.evil

Joined Aug 18, 2010
80
I fiddled around with the R2/R3/R4 values, and with R2=20Ω, R3=220Ω, R4=10Ω I get the following sim result:
Screenshot from 2017-11-29 14-03-19.png

I still don't know why Q2 rise/fall times are so huge? It's a transistor...!
 

Alec_t

Joined Sep 17, 2013
10,746
The transistor junction capacitances are the likely culprits.
Try this mod, using a totem-pole pair of bjts to drive the output transistor Q4. Note the addition of D2 and D3 to assist turn-off of Q4.
ShortPulseGen.PNG
 

recklessrog

Joined May 23, 2013
985
Just a thought, There is no bias for Q1 other than the output from the signal generator, you need current into the base so If the output generator is via a large capacitor, this may be charging up to an average DC level causing the blue waveform to appear as it does in your first picture of it with the rising base line from 0 Volts to 5 Volts.
 

Thread Starter

dr.evil

Joined Aug 18, 2010
80
Just a thought, There is no bias for Q1 other than the output from the signal generator, you need current into the base so If the output generator is via a large capacitor, this may be charging up to an average DC level causing the blue waveform to appear as it does in your first picture of it with the rising base line from 0 Volts to 5 Volts.
Correct, but what is not shown is that the signal generator output is actually a CMOS gate with 20mA source/sink. Maybe I should add that.
 

crutschow

Joined Mar 14, 2008
24,130
I scrapped it feeling confident that I would be able to replicate the behavior starting from scratch.
So what was this magical circuit that you scrapped?

Does the load have to be grounded or can it be high-side driven?
I still don't know why Q2 rise/fall times are so huge? It's a transistor...!
And transistors have finite rise and fall times.
Why do you think that's unusual?
 

Thread Starter

dr.evil

Joined Aug 18, 2010
80
The transistor junction capacitances are the likely culprits.
Try this mod, using a totem-pole pair of bjts to drive the output transistor Q4. Note the addition of D2 and D3 to assist turn-off of Q4.
View attachment 140481
Yes, that's more like it, actually mr. crutschow suggested something along those lines, but the context was increasing current through R5.

This is my new sim result, now I have to see what can be done with the trans-sisters I have physically available and solder it together:
Screenshot from 2017-11-29 17-43-52.png
 

Thread Starter

dr.evil

Joined Aug 18, 2010
80
So what was this magical circuit that you scrapped?
I don't know, I forgot about it, didn't make any notes along the way as I thought I would never use it. I don't think it was "magical" though.

Does the load have to be grounded or can it be high-side driven?
It has to be grounded.

And transistors have finite rise and fall times. Why do you think that's unusual
I do not find it unusual that transistors have finite rise and fall times. I find it unusual/odd/puzzling that the rise/fall time of Q2 shows something like 1V/20ns, when a logic gate (that has transistors in the output stage) do it much much faster. Logic dictates that there is something unusual/odd/puzzling, that be by my own ineptitude or something else.
 

KL7AJ

Joined Nov 4, 2008
2,225
Gent,

I took all the advise I got from my previous thread and incorporated them into my circuit, but I still can't get some clean switching, this is my circuit du jour, including calculated DC Bias (credit goes to partsim.com):
View attachment 140413
Datasheet for NSS40300MZ4
And this is the transient analysis of PULSE, where ORANGE is left side of R4, and RED is base of Q2, and BLUE is collector of Q2:
View attachment 140414 And this is the reality, RED is base of Q2, and BLUE is collector of Q2 (only got a two channel sillyscope). 100mV/div and 500ns/div. Both are AC measurements
View attachment 140415
And this is part of reality too, RED is is left side of R4, 4V/div and 500ns/div (DC measurement):
View attachment 140418

I don't get it, why wont Q2 switch off properly? and why is the pulse distorted?
Looks like you could use better power rail decoupling.
 

crutschow

Joined Mar 14, 2008
24,130
a logic gate (that has transistors in the output stage) do it much much faster.
The difference is that the tiny transistors in a logic gate that control mA will switch much faster than a large transistor that has to switch amps.
Among other things, it's a matter of the number of carriers in the transistor that have to be turned on and off, and the distance these carriers have to travel in the semiconductor.
 

Thread Starter

dr.evil

Joined Aug 18, 2010
80
The difference is that the tiny transistors in a logic gate that control mA will switch much faster than a large transistor that has to switch amps.
Among other things, it's a matter of the number of carriers in the transistor that have to be turned on and off, and the distance these carriers have to travel in the semiconductor.
My dear Mr. crutschow, I unequivocally agree with you, no doubt! However the circuit, in it's present stage, does not switch amps, therefore I believe that my personal conundrum still carries some validity.
 

crutschow

Joined Mar 14, 2008
24,130
My dear Mr. crutschow, I unequivocally agree with you, no doubt! However the circuit, in it's present stage, does not switch amps, therefore I believe that my personal conundrum still carries some validity.
But the output transistor is still large.

As I previously noted, if you want to generate such a fast pulse it likely will be easier with a push-pull driver to control the gate of a P-MOSFET.
You are somewhat beating a dead horse here. :rolleyes:
 

crutschow

Joined Mar 14, 2008
24,130
Sorry about that, it was not my intention. What do you suggest I do? Delete the thread? Mark it "solved"?
It's up to you.
I don't think you can readily get the circuit as you have it, do what you want, so It would seem you should go to a better circuit.
But you seem to want to continue with one that doesn't (hence the dead horse analogy).
 

Thread Starter

dr.evil

Joined Aug 18, 2010
80
It's up to you.
I don't think you can readily get the circuit as you have it, do what you want, so It would seem you should go to a better circuit.
But you seem to want to continue with one that doesn't (hence the dead horse analogy).
My dear Mr.crutschow. Firstly I appreciate and value your input, I don't want that you think that I'm ungrateful in any way for the competent input I'm getting here at AAC. That being said, for your analogy to be valid, your premise must be that I do not know; where I'm coming from, where I'm going and how to get there, you may rest assured that it is absolutely not the case.

Regarding your FET proposal, I have some reservations about it for this application, I had trouble sourcing a FET capable of handling the current without it having a fly-back diode and a high (>2Ω) RDS(on) at those voltages. But obviously that was in my pre-Farnell days, maybe you can suggest a candidate? That would be helpful.
 
Top