Hi,

As discussed here one can add a pull-down resistor to the floating/outboard leg of a coupling capacitor to pull it to the negative rail. This is supposed to eliminate switching noise. The article states that, barring leakage, this outboard leg would normally be 0V. Is that true? Wouldn't that depend on the state of charge at the moment the cap got disconnected?

And why pull to the negative rail? The signal lives somewhere mid-rail. When the cap is switched in again it quickly needs to charge from 0V to ~4.5V. So why not pull this outboard leg to mid-rail?

 

There is missing information such as: "Is there any DC bias on the input device and the output device?"

So let's delve in this a little deeper.
What is the purpose of the pull-down resistor?
Is it to eliminate pops when the stop box is switched in-line?

To eliminate pops we need to know the output circuitry of the sound source and similarly the input circuitry of the receiving device. All series coupling capacitors must be pre-charged to a steady-state condition so that no current flows when the device is switched in and out.

There is no one-solution-fits-all until we know how the sending and receiving devices are designed.

 

"Is there any DC bias on the input device and the output device?"

Suppose it's in the middle of an effects chain, then at the input there would be a signal biased to mid-rail. The output could be the next pedal or the input of the amplifier.

What is the purpose of the pull-down resistor?
Is it to eliminate pops when the stop box is switched in-line?

In general I would like to understand how to make a stomp box that doesn't pop, switching in and out. Allegedly such a pull-down resistor would do the trick but I don't understand why it would. In fact, I would expect it to make things worse because now the cap is at 0V and the soon to be switched in signal is at 4.5V. Yet this advise (adding a pull-down) is found all over the internet.

To eliminate pops we need to know the output circuitry of the sound source and similarly the input circuitry of the receiving device. All series coupling capacitors must be pre-charged to a steady-state condition so that no current flows when the device is switched in and out.

There is no one-solution-fits-all until we know how the sending and receiving devices are designed.

I see. It's difficult to know for at least some of the stuff in the chain. I guess if I only switch the input and not the output then that's one less coupling cap to worry about. What do you think about pre-charging to mid-rail?

I'm sorry the somewhat unspecific answers to some of your questions, but then I do not know.

 

What is the purpose of the diodes at the JFET gates here? Can they not be omitted?

 

The circuit schematic is confusing.
Vr is half the supply voltage.
The final output transistor shows no connection to a signal except Vr.
It is not clear what is SW.

 

You're right, that doesn't look correct. The SW is just a momentary switch I think. Edit: Ah, I see what SW you refer too. I have no idea.

Like the circuit below. It has a momentary foot switch followed by a debounce circuit and then some kind of flipflop. The flipflop then switches Q9 in or out, hopefully without popping. But I don't understand why D4 is in series with the gate of Q9.

 

Behold my ignorance.

Edit: asc attached. I still don't see the point of the diode.

 

Thetwo FET devices in the post#4 circuit switch the output stage to either the input or the end of the effects section.How would it work if they were eliminated?? I see no way to get around needing them, or an equivalent. The momentary switch toggles the flipflop, (a bistable multivibrator) that selects bypass or through. There are alternatives that would use digital integrated circuits, another option. The FET devices are not gates in the normal sense, but simply being used as switches.

 

How would it work if they were eliminated?? I see no way to get around needing them, or an equivalent.

I don't know. The other part of my question was "What is the purpose of the diodes at the JFET gates here?". So, what is the purpose of the diodes at the JFET gates here?

If you pull the gate low and V_GS = -4.5V the JFET is off, no signal passes.
If V_GS = 0V the JFET is on, signal passes.
What happens to a JFET when V_GS becomes positive? Is the diode there to prevent that somehow?

 

hi hrs,
Checking your LTS sim I don't see any purpose for the gate diode, when using a 2N3819.?
Perhaps the original designer, when using a 2SK30A FET did have a problem.?

E

 

Hi Eric,

Possibly my sim fails to capture the essence of an audio switch like this. For one I see that I connected C1 to the wrong end of R1.
Maybe @MisterBill2 can explain.

 

You're right, that doesn't look correct. The SW is just a momentary switch I think. Edit: Ah, I see what SW you refer too. I have no idea.

Like the circuit below. It has a momentary foot switch followed by a debounce circuit and then some kind of flipflop. The flipflop then switches Q9 in or out, hopefully without popping. But I don't understand why D4 is in series with the gate of Q9.

D4 is there so that the gate of the JFET doesn't get forward biased when the flip flop goes high.

 

The diode, D4, is in series to avoid any positive transition of the gate from causing a "pop" in the signal when the gate pull down voltage is removed. At least that is what I see it as doing.

 

D4 is there so that the gate of the JFET doesn't get forward biased when the flip flop goes high.

Regarding the schematic in post #6, if the flipflop goes high and after C28 is done charging then there will be very little current through R49 and the cathode of D4 will get pulled close to the positive rail and the anode side will float up as well, would you agree? Then, with D and S at ~4.5V, the JFET would be forward biased, however D4 prevents any current from flowing through the gate. Or is that the same thing, no current flowing means it's not forward biased?

If the diode prevents the gate from going above ~4.5V then I don't understand why that is. But if it's just there to block the current then I get it. There's not much I can find about forward biased JFETs except that you shouldn't.

Edit: Or the gate current is much greater than the diode leakage and therefore the diode effectively clamps the gate to ~4.5V, that is probably it.