Hello there,

There is a formula:
G=0.5*C2/(C1+C2)*(GAIN OF CONTINUOUS INTEGRATOR AT INPUT FREQUENCY)

that is supposedly an approximation for the gain of a non inverting switched capacitor integrator.

So far every calculation seems to point to that first part being:
C1/C2

rather than:
0.5*C2/(C1+C2)

but the formula came from a professor so we think it might be true.

Anyone have any experience with this, or with switched capacitor integrators in general such that you might shed some light on this 'new' formula?

I can provide the circuit diagram if necessary. It's a simple circuit where the second cap C2 is always the feedback across an op amp (output to inverting terminal) and the input cap C1 is either connected to the inverting terminal to ground (phase 2 of the clock) or directly across the input voltage (phase 1 of the clock). C1's polarity is such that it is connected normally across the input for phase 1 and connected backwards during phase 2 of the clock so that the output of the op amp is positive with a positive input voltage (and thus non inverting). There are no other components other than the switches that change the connections for both leads of C1.

Thanks

 

Switched capacitor circuits are a very common part of the circuits I've designed. There are many different topologies to achieve most goals, you really need to include a schematic of what you are talking about, including the switches.

In general, the combination of the caps and the switches result in an effective resistance between the nodes because, for a given voltage difference, you will achieve an average current flow that is proportional to the product of the capacitor size and switching frequency (and note that the units on the reciprocal of the product of the capacitor size and the switching frequency are ohms).

 

Hi there,

Hey thanks for the reply.

Here is the circuit...
Also note that i had to correct the formula given in the original post due to a small typo.

Thanks

 

IMO the Prof's formula applies to a different integrator configuration than the one in your attachment, perhaps where C1 and C2 get connected temporarily in parallel to share charge, which would give a combined capacitance of C1*C2/(C1 + C2).
In the integrator you show, a charge dq=C1*V(in) is transferred to C2 in each pulse period. Therefore C2 voltage increases by dV(out) = dq/C2 = V(in)*C1/C2. Therefore V(out) at time t = (C1/C2)*V(in)*f*t, where f is the pulse frequency.

 

Here is the circuit...

Note that C2 is not switched, it is merely the feedback element as thus forms an integrator in which the output voltage is the integral of the input current (the current into negative terminal of C2) with a transfer function of

\(
v_{out}(t) \; = \; -\frac{Q_2}{C_2} \; = \; -\frac{1}{C_2}\int_{-\infty}^{t}I_{in}(t) dt
\)

So we just need the expression for Iin(t).

When Φ1 is active, S1 and S3 are closed (the others are open), so an amount of charge is placed on C1 equal to

\(
q_1 \; = \; v_{in}(T_0) \cdot C_1
\)

When Φ2 goes active, S2 and S4 are closed (the others are open), and the opamp can only make the differential input voltage is sees be zero by changing the output voltage so as to draw all of the charge on C1 off (since when the inverting input of the op amp is zero (to match the noninverting input) and the positive side of C1 is zero (due to S2) there isn't any charge on C1).
To do this, it actually has to drive the charge back out the positive terminal of C1 which means driving charge into the negative terminal of C1 which required that the output of the opamp go positive (if Vin is positive) to drive current into the positive terminal of C2.

You can think of this as a push-pull effect -- Vin single pushes a packet of charge into C1 on one phase of the clock and Vout pushes that charge back out on the other phase.

If the time for one cycle is T, then we have

\(
i_{in_{avg}}(T_0) \; = \; \frac{Q_1}{T} \; = \; v_{in}(T_0)\frac{C_1}{T}
\)

T is simply the period of the switch clocks and is 1/Fs.

\(
i_{in_{avg}} \; = \; V_{in} \(C_1 F_s \)
\)

Notice that we can equate this with an effective input resistance of

\(
R_{in} \; = \; \frac{V_{in}}{I_{in_{avg}}} \; = \; \frac{1}{C_1 F_s}
\)

The smaller the capacitance the larger the resistance, which makes sense since a smaller amount of charge is transferred each cycle. Also, the lower the frequency the larger the resistance, which makes sense since charge is transferred a fewer number of times in any given period.

However, while this is the effective input resistance seen by the input signal, it is not quite the effective input resistance compared to a classical RC opamp integrator. The effective resistance for that purpose is actual -Rin because of the push/pull effect descripted earlier.

\(
v_{out}(t) \; = -\frac{1}{C_2}\int_{-\infty}^{t}I_{in}(t) dt
\;
v_{out}(t) \; = -\frac{1}{C_2}\int_{-\infty}^{t}\frac{v_{in}}{-R_{in}}(t) dt
\;
v_{out}(t) \; = \frac{1}{C_2}\int_{-\infty}^{t}v_{in} \cdot C_1 F_s(t) dt
\;
v_{out}(t) \; = \frac{C_1}{C_2} F_s \int_{-\infty}^{t}v_{in}(t) dt
\)

This is strictly true only if the input voltage is constant during each clock period at the level at which it is sampled at the end of the clock period. As long as the clock frequency is fast enough for this to be a reasonable approximation, we are okay. This places a practical upper limit on how high we can make the effective input resistance.

 

IMO the Prof's formula applies to a different integrator configuration than the one in your attachment, perhaps where C1 and C2 get connected temporarily in parallel to share charge, which would give a combined capacitance of C1*C2/(C1 + C2).
In the integrator you show, a charge dq=C1*V(in) is transferred to C2 in each pulse period. Therefore C2 voltage increases by dV(out) = dq/C2 = V(in)*C1/C2. Therefore V(out) at time t = (C1/C2)*V(in)*f*t, where f is the pulse frequency.

(1) the output is inverted relative to the input.

(2) the output is related to the integral of V(in), which is V(in)·t only if V(in) is a constant.

 

the output is inverted relative to the input.

Not so for the post #3 circuit. If Vin is +ve, the inverting input of the amp gets pulled down when S2 and S4 close, but the amp counters this by driving its output +ve.

 

Not so for the post #3 circuit. If Vin is +ve, the inverting input of the amp gets pulled down when S2 and S4 close, but the amp counters this by driving its output +ve.

You are correct. This is a slightly different configuration that I usually worked with and I made a mental goof when looking at it. I'll patch my post accordingly.

 

IMO the Prof's formula applies to a different integrator configuration than the one in your attachment, perhaps where C1 and C2 get connected temporarily in parallel to share charge, which would give a combined capacitance of C1*C2/(C1 + C2).
In the integrator you show, a charge dq=C1*V(in) is transferred to C2 in each pulse period. Therefore C2 voltage increases by dV(out) = dq/C2 = V(in)*C1/C2. Therefore V(out) at time t = (C1/C2)*V(in)*f*t, where f is the pulse frequency.

Hi Alec,

That would make a lot of sense. With the current schematic there seems to be no way to obtain a partial gain factor of C2/(C1+C2). In another forum i did a simulation of that circuit in the schematic and the gain factor is much, much closer to C1/C2 than it is to C2/(C1+C2). I will wait for WBahn's final analysis before making a final judgement.

I find these filters quite interesting, but it's been a very long time since i had to look at the theory behind them.

 

I've already patched by prior post -- hopefully I walked the corrections through correctly. If anyone sees something that I overlooked I will be happy to revise it.

 

Hello again,

Thanks for the reply.

The next step then is to try to eliminate the switched cap integrator altogether and replace it with a continuous integrator and additional gain factor, and have the gain of both circuits come out the same. This means calculating the gain of the continuous integrator and then another gain that when multiplied times the continuous integrator gain provides the same overall gain as the switched capacitor integrator. This is the whole point of the exercise. The additional gain factor should be formed from the component values and possibly another constant gain like 1/2.

 

IMO the first step would be to identify the ciruit configuration used to obtain the C2/(C1+C2) factor. It clearly wasn't the configuration shown. I suspect it was a more elaborate version of this one.

 

Here's a configuration which places C1 and C2 in parallel.

The sim was run for three values of C2. The curves V(out1) and V(out2) respectively for the switched-cap and continuous integrator (modelled by B1) coincide perfectly when the B1 gain factor is f*C1/(C1+C2). Not what the Prof got, but similar . I don't see where his 0.5 factor comes from.

Edit: R1 and C3 are for cosmetic reasons; they merely remove some switching spikes to tidy up the waveform.

 

Hi,

Yes there has to be more to it than this. I am awaiting more input on this from the source.
There is even a chance that he meant that the CONTINUOUS INTEGRATOR GAIN we supposed to be the OPEN LOOP GAIN, but i have to wait for a reply before i'll know for sure.
Will be interesting to find out.