Hello everyone!
I am now designing a switched-capacitor (SC) bandgap reference, but I am having doubt on the switches size that I should use.
Let say I do not have any issue with settling time and my op-amp is good enough about slew rate and response time.
Regardless of how is the structure of my SC bandgap, I am just asking a general question.
What kind of size I should set for my switches? Is it okay to put the minimum size of W/L?
Let say my process is 0.18um, can I put the switches' size to be all 0.18um/0.18um?
Let say I use all switches to be NMOS.
The reason why I want minimum is to minimize charge injection, because my charge injection is still very bad affecting my node voltages when the switches are turned off. (even with that old-school book of using half-sized NMOS with S+D connected.)
I noticed that when I put that 0.18u/0.18u size to all my switches, my deltaV as impact of switching on/off at my nodes are reduced.
When I say reduced, it is still 10-20mV change (higher or lower) in node voltage when the switches turn off (even with minimum size). If i use higher W, that deltaV could be in hundreds of mV range. Even this 20mV is kind of unacceptable since I am designing bandgap reference.
Would any Master here give me advice please? Is it okay to use minimum size of NMOS to all your switches in your SC circuit design? Because my friend is not convinced that this kind of minimum size NMOS switches are used in the real practice by others.
Anyone know any reference (research paper or something) that people design SC circuits with minimum size NMOS?
So far all the papers that I am reading, they don't talk about using minimum size of switches at the SC circuit design.
I would highly appreciate your kind help and answer!
Thank you!
I am now designing a switched-capacitor (SC) bandgap reference, but I am having doubt on the switches size that I should use.
Let say I do not have any issue with settling time and my op-amp is good enough about slew rate and response time.
Regardless of how is the structure of my SC bandgap, I am just asking a general question.
What kind of size I should set for my switches? Is it okay to put the minimum size of W/L?
Let say my process is 0.18um, can I put the switches' size to be all 0.18um/0.18um?
Let say I use all switches to be NMOS.
The reason why I want minimum is to minimize charge injection, because my charge injection is still very bad affecting my node voltages when the switches are turned off. (even with that old-school book of using half-sized NMOS with S+D connected.)
I noticed that when I put that 0.18u/0.18u size to all my switches, my deltaV as impact of switching on/off at my nodes are reduced.
When I say reduced, it is still 10-20mV change (higher or lower) in node voltage when the switches turn off (even with minimum size). If i use higher W, that deltaV could be in hundreds of mV range. Even this 20mV is kind of unacceptable since I am designing bandgap reference.
Would any Master here give me advice please? Is it okay to use minimum size of NMOS to all your switches in your SC circuit design? Because my friend is not convinced that this kind of minimum size NMOS switches are used in the real practice by others.
Anyone know any reference (research paper or something) that people design SC circuits with minimum size NMOS?
So far all the papers that I am reading, they don't talk about using minimum size of switches at the SC circuit design.
I would highly appreciate your kind help and answer!
Thank you!