SRAM simulation in LT Spice

Thread Starter

anju_john

Joined Mar 17, 2016
12
Hi ,
I am simulating the read and write operations of a 6T SRAM cell using LTSpice. But, i am not getting a proper output. The simulation results shows that the output (stored bits) changes with bitline even if the word line is low. Why it is so?

The transistor (nmos ) output depends on the gate voltage right? Then why it changes with bitline?

these are the results i got...

Capture.JPG nmos.JPG sram.JPG sram_result.JPG

Please help me.
Thank you
 

ronv

Joined Nov 12, 2008
3,770
Hi ,
I am simulating the read and write operations of a 6T SRAM cell using LTSpice. But, i am not getting a proper output. The simulation results shows that the output (stored bits) changes with bitline even if the word line is low. Why it is so?

The transistor (nmos ) output depends on the gate voltage right? Then why it changes with bitline?

these are the results i got...

View attachment 102614 View attachment 102615 View attachment 102616 View attachment 102617

Please help me.
Thank you
I think you need to use a "real" FET and not the generic one. You can do this by right clicking the FET and picking one from the standard library.
If this doesn't work post your .esc files.
 

Thread Starter

anju_john

Joined Mar 17, 2016
12
I think you need to use a "real" FET and not the generic one. You can do this by right clicking the FET and picking one from the standard library.
If this doesn't work post your .esc files.

Thank you for the reply. I tried with real FET. But still the same problem. i have attached the file
 

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kubeek

Joined Sep 20, 2005
5,724
Apparently it overrides the default value of the parasitic resistance that is parallel to the capacitor, so that the capacitor has lower leakage than it would with default value.
 

Thread Starter

anju_john

Joined Mar 17, 2016
12
Apparently it overrides the default value of the parasitic resistance that is parallel to the capacitor, so that the capacitor has lower leakage than it would with default value.
Thank you..
Could you please tell me how to find the static noise margin of a sram cell in ltspice. i tried with the attached .sp file. but it is showing the errors BITCAP is not defined and U is not a source or temp. How can i resolve these errors.
 

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Thread Starter

anju_john

Joined Mar 17, 2016
12
Learn the syntax LTspice. Your file claims the Hspice syntax.
Sure, i will try to learn it. Actually i tried to modify my schematic file for the snm analysis. Is it possible to do in this way, since i am not much familiar with the software. Also, how to give those equations to the sources in a schematic.
 

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Thread Starter

anju_john

Joined Mar 17, 2016
12
I fixed all your syntax errors. I do not understand your goals and what you do, and because nothing else did.
Thank you so much. Actually my goal is to analyse the static noise margin of a 6T sram cell. For that i need to plot the butterfly curves and to measure the highest possible square inside the loops. When i referred some research papers, i saw that we need to mirror the inverted characteristics to get butterfly curves. i tried with dc sweep including two noise sources. but it was like nested sweep and i got some wrong results. so i modified the schematic based on some spice codes. here also i am getting only one proper curve. Since i am not much familiar and beginner in ltspice, i dont know the other possibilities. This is the actual problem. how can i mirror the inverter characteristics in order to measure snm.

I need to get a graph as attached here
 

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kubeek

Joined Sep 20, 2005
5,724
the two curves you showed don´t look like any kind of mirror image. Shoouldnt you just ramp the x axix back and forth and graph y axis?
 
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