I have gone through Wikipedia page https://en.wikipedia.org/wiki/Serial_Peripheral_Interface

I'm having a bit of difficulty to understand SPI number mode in this page

 

hi John,
Checkout section 23.3 of this PDF. ask if you have a query.
E

 

hi John,
Checkout section 23.3 of this PDF. ask if you have a query.
E

Is there any easier documents other then this ?

SPI mode configure CKP, CKE and SMP bits.
CKP: Clock Polarity Select bit
CKE: SPIx Clock Edge Select bit
SMP: SPIx Data Input Sample Phase bit

 

hi John,
Is this better.?

E

 

hi John,
Is this better.?

SPI interface allows to transmit and receive data simultaneously on two lines (MOSI and MISO). Clock polarity (CPOL) and clock phase (CPHA) are the main parameters that define a clock format to be used by the SPI bus

SPI has four modes (0,1,2,3)

Mode 0
CPOL=0, data valid on the low-high transition.
CPHA=0 data is sampled on the low -high transition of the clock.

Mode 1
CPOL=0, data valid on the high-low transition.
CPHA=0 data is sampled on the high -low transition of the clock.

What are the mode 2 and mode 3 ?

 

hi J.
Look thru this link.
CPOL is clock polarity in the pre transfer state
CPHA is the data sampling phase

https://www.corelis.com/education/tutorials/spi-tutorial/

 

When configuring SPI master and slave devices, you need to specify the relative phase between the clock and data signals.
There are two parameters to set, CPOL and CPHA.
CPOL has two values 0 and 1.
CPHA has two values 0 and 1.
Hence there are four possibilities, called modes:

SPI Mode | CPOL | CPHA
0 = 0 0
1 = 0 1
2 = 1 0
3 = 1 1



Mode 0, CPOL = 0, CPHA = 0
SCK idles at 0, goes 1-0
Master sets first data bit and then sends SCK = 1.
Master sets next data bit and SCK = 0.
Slave clocks data in on the rising edge of the clock

Mode 1, CPOL = 0, CPHA = 1
SCK idles at 0, goes 1-0
Master clocks data out on the rising edge of the clock
Slave clocks data in on the falling edge of the clock

Mode 2, CPOL = 1 CPHA = 0
Same as Mode 0 except SCK is inverted
SCK idles at 1, goes 0-1
Master sets first data bit and the then sends SCK = 0.
Master sets next bit and SCK = 1.
Slave clocks data in on the falling edge of the clock.

Mode 3, CPOL = 1, CPHA = 1
Same as Mode1 except SCK is inverted
SCK idles at 1, goes 0-1
Master clocks data out on the falling edge of the clock
Slave clocks data in on the rising edge of the clock

https://en.wikipedia.org/wiki/Serial_Peripheral_Interface

 

Since you (TS) refer to CKE, I am assuming you are using a PIC device. Here is a section of code I routinely add. It facilitates, at least for me, setting a mode when 2 or more devices used different modes. NB: CKE is the inverse of CPHA.

;*******************************************************************************
;Setup SPI serial port
;*******************************************************************************
;;Mode 0                      ;CKP=0, CKE=1
;     banksel   SSPSTAT       ;16F1783 DS refers to these registers as shown  |B4
;     clrf      SSPSTAT       ;but the text omits the "1's", works either way |B4
;     bsf       SSPSTAT,6     ;CKE=1 =active to idle                          |B4
;     movlw     b'00100001'    ;SPI clk=Fosc/4,bit<0>=0,clk=Fosc/16,bit<0>=1  |B4
;     movwf     SSPCON1        ;bit<4>,CKP=0 = idle low, bit<5> enables SPI   |B4
    
;;Mode 1                      ;CKP=0,CKE=0
;     banksel   SSPSTAT       ;all SPI controls in Bank4                      |B4
;     clrf      SSPSTAT       ;CKE=0, SMP=0 (sample at middle)                |B4
;     movlw     b'00100001'    ;enable SPEN, set SPI CLK to Fosc/16           |B4
;     movwf     SSPCON1       ;CKP=0,master clk =Fosc/x (see below)           |B4

;;Mode 2                      ;CKP=1,CKE=1                     
;     banksel   SSPSTAT       ;all SPI controls in Bank4                      |B4
;     clrf      SSPSTAT       ;CKE=1, SMP=1 (sample at middle)                |B4
;     bsf       SSPSTAT,6     ;                                               |B4   
;     movlw     b'00110001'    ;enable SPEN, set SPI CLK to Fosc/16           |B4
;     movwf     SSPCON1       ;CKP=1,master clk =Fosc/x (see below)           |B4

;;Mode3                       ;CKP=1,CKE=0
     banksel   SSPSTAT       ;                                               |B4
     clrf      SSPSTAT       ;                                               |B4
     movlw     b'00110001'   ;enable serial port, clk = Fosc/16              |B4
     movwf     SSPCON1       ;                                               |B4
;*******************************************************************************
     bsf       SSPSTAT,7      ;set SMP, doess not affect mode              |B4