Hey yall. I am very new to digital design and now I am trying to make a binary(ABCD) to 7segment decoder. My problem is how I can simplify the circuit as much as possible. I have to make it in the way that the output values of 10 and 11 have to be low allover, and the rest(12,13,14,15) is "dont care".

Ok, karnaugh maps are understandable, and I get my expressions based on the truth table. The thing is that I want it to be smaller.

Using Karnaugh map, I get approximetly 24-26 gates. Although I have heard that it is possible to get the circuit down to 16-17 gates. So my question is how I can simplify the circuit even more?
I tried using boolean algebra, but I think it demands some speciall skills or tricks to simplify this circuit even more. My book does not cover any tricks on handeling situations like the one I described. The book only covers the theorems and axioms.

I appriciate all the help I can get. I am looking for links, info, anything.

 

Hi,

I always try not to reinvent the wheel. I hauled out my Schottky TTL manual and looked up a 74LS48. The internal logic has about 36 gates, but some appear to be inverters and logic for blanking. My guess is that the ic designers made things as simple as possible. You might give one a look-over.

 

I just looked at one manual, and I noticed that the chip you described has a different truth table then what I described.

" I have to make it in the way that the output values of 10 and 11 have to be low allover, and the rest(12,13,14,15) is "dont care"."

I belive that the designer of the 74LS48 used that much more gates because the truth table of 74LS48 has almost no "dont care" outputs.

So is it possible to simplify even more then Karnaugh maps?

 

Hi,

No, Mr. K gives the simplest implementation. I just offered an operating device.

You can see where eliminating the test and blanking functions will reduce gates. Also, adding the gates to stop an output for values 10 and 11 are an easy step.

 

Hmm.. I think I have to talk to my proffessor and ask him what he ment with tricks for simpliying the expression even more then k-map.

Is it possible to use special design technics when designing the circuit with the expressions from the k-map so that the design uses less gates the what the k-map produced? (Not thinking of boolean algebra here)

One thing I used was off course to reuse one gate combination if two or of the same gate combinations occure in the expressions from the k-map. Are there other things like this I can do to make use of less gates? But this only gave me 4 gates less.

 

Hi,

If it works the way you want, then it's ok. You're only concerned with the number of gates, not the number of ic's.

 

Actually its not just about working. It is easy to make the thing work, but it is hard to make it work while using less gates. See the thing is that a NAND and an inverter are looked upon as one gate regardless of how many transistors they use. So I have many types of gates in my aresenal, like XOR etc.

The thing is that it is only going to be simulated on PC so IC's are not an issue in my case.

I noticed that the 74LS48 is made of almost AND gates, so dont you think the designer might have needed less gates if he\she used other gates as well?

 

Try starting with the 74HC511, they are still available.

 

What gates exactly are you allowed to use? And how many inputs can you have on one gate? This is an artificial problem, and as far as I can see, it's not fully defined here.

K-maps work with AND/OR/NOT, so it is true that you can sometimes get "less gates" by substituting an XOR.