Hello,
I write since I have a problem with the Tang nano 9k by Sipeed. I am working on a research project about analog measurements without an ADC and I am investigating the properties of high impedance input pins of microcontrollers and FPGAs to behave like a threshold comparator for analog voltages (i.e. if I apply an analog volatge Van to a digital input pin, then the digital value of this pin is read as 1 if Van > VIH and is read as 0 if Van < VIL). In this first stage of the research project I am measuring VIH and VIL for different microcontrollers and FPGA devices.
My experimental setup is as follows: a Nucleo L073 microcontroller board (that integrates a 12-bit DAC inside the microcontroller) is used to generate the analog voltage Van that is fed to an input pin of the device under test (another microcontroller or FPGA board). GND for the Nucleo board and the device under test are shorted together. The device under test generates a digital output corresponding to the digital input that is sent to a digital input of the Nucleo board. The Nucleo board is programmed to generate increasing (and then decreasing) values of the DAC output (Van) and to read the digital output value of the device under test. This way, the values of VIH and VIL are measured.
This experimental setup works correctly with different systems: ST Microelectronics Nucleo boards, Arduino Due board, as well as some Xilinx FPGA boards (Basys 3 and Zybo). When I test it with the Tang nano 9k FPGA board, however, something strange happens. If I give the analog signal Van to a digital input pin and generate a digital output Vout with a NOT gate (i.e. NOT input Van, NOT output Vout), the output Vout is not stable and oscillates between 0 and 1 when it should be 1, while it is stable when it should be 0. I have tried with different options for the output pin (high impedance, pull-up, pull-down, keeper) but the result is always the same. I do not think the FPGA board is damaged since if I use digital signals (instead of the analog voltage Van) all works correctly and I have tried some simple projects involving digital signals without problems.
Can anyone help me to understand why tang nano 9k behaves this way and if the problem can be solved?
Thanks.
Marco

 

HI assume that the Nucleo board DAC output a PWM signal. How well is it smoothed? If the Tang nano has inputs that do not have much hysteresis, they may be toggling on the ripple on the input signal.

 

Hi. The Nucleo board outputs an analog signal (0:3.3V programmable by firmware) and not a PWM signal since it integrates a 12-bit DAC. The experimental setup works correctly with the Xilinx FPGA Basys 3 and Zybo that are characterized by a lower hysteresis than the Tang nano 9k.