Alright, I need someone to school me on this subject. I have a circuit that I am designing for a clock distribution system to take a differential input to a single ended output. The input is a 0-5v differential driver (square wave). The amp has a gain of 2 to account for the input termination.

I am having trouble with the case where 0 volts is applied to Clock_P and 5v is applied to Clock_N. In this case the op amp output should saturate to the negative supply, thus providing a logic low. Is this unreliable/bad practice? Please explain, thanks!

 

The LMH6601 is rail to rail on the output only. The inputs are limited to +V -1.5 volts and the maximum differential voltage is 2.5 volts. At a gain of 2 you are exceeding these voltages.

 

Thanks for the response. So consider the setup where the differential drivers have 50 ohm output impedance (balanced line, right?). In this case there should only be ~2.5v differential across the input terminating resistor, Rt, correct?

So in the scenario of a logic high there will be +2.5v as measured across Rt from the non-inverting to the inverting input. This gives an output of +5v.
In the logic low scenario, there will be +2.5v as measured across Rt from the inverting to the non-inverting input. You are telling me this violates the input voltage limit? I believe this +2.5v at the inverting input will drive the output to -5v, but because it is single supply it will saturate at ~0v. And my question is: is this poor practice to rely on the op-amp to saturate the output to the ground rail?

 

OK, I see what you are getting to, but in your first post you specified the actual voltages at the input pins at zero and 5 volts. These voltages would over drive the diff amp into a non-linear region.

As far as you getting an input voltage drop due to the source and load resistances, is this what you are expecting to happen or something you have measured? Do you have control of the differential driver design? Specifically, what are the symptoms of the problem?

 

Ah, sorry. This is my expectation. I ran a spice simulation and it behaved as I expected, with an output of 5v (High) and 0v (Low). I have some input as to the differential driver - another guy is handling that design. He told me that he didn't think this design would work because I'm relying on the op-amp to saturate at 0v when I'm driving it outside of its linear range. But I thought that's what op amps are supposed to do!

 

The newer rail to rail input and output op-amps will perform that way if you limit the input current. I generally will not use that "feature" of an op-amp unless it is specifically called out in an app note.

Why did you not use a conventional LVDS, or similar, differential driver/receiver set? They are a well supported.

 

Originally I had planned on using an rs485 receiver. But the output needs to be able to support a 50 ohm terminator, meaning 100+ mA of current. So I looked into adding a FET driver to the receiver, but was told that they added too much delay/jitter to the clock signal. I think it is still an option if I can convince them it would produce comparable performance. It is definitely simpler.

Could you recommend any nice, high power drivers/buffers?

 

Your clock and data lines should have the same receiver components to minimize delays. There are a lot of 5 volt driver/buffers out there. What is your data transfer rate? Rise and fall time?

You could just go to the TI website and look around their "interface" section. A lot of options there.

 

I have a circuit that I am designing for a clock distribution system to take a differential input to a single ended output. The input is a 0-5v differential driver (square wave).

I am having trouble with the case where 0 volts is applied to Clock_P and 5v is applied to Clock_N. In this case the op amp output should saturate to the negative supply, thus providing a logic low.

I think it would be easier to use a comparator, instead of an op-amp.