I don't think this circuit needs a delay.

We need to figure out why M1 is hanging up on the transition.

My suspicion is due to the Darlington high side output of the 555 causing the gate of M1 to not be discharged quickly enough.

I believe the model for the 555 in LTSpice is ideal and this kind of problem would never show up in the sim.

 

I
View attachment 321484

Hmmmmm…. 404

 

I don't think this circuit needs a delay.

It does if you want to guarantee a non-overlap of the two signals.

believe the model for the 555 in LTSpice is ideal

The NE555 is ideal, but the NE555-1 is a transistor model version.

 

Hmmmmm…. 404

Hmmmmm.... Corrected

 

I don't think this circuit needs a delay.

We need to figure out why M1 is hanging up on the transition.
S
My suspicion is due to the Darlington high side output of the 555 causing the gate of M1 to not be discharged quickly enough.

I believe the model for the 555 in LTSpice is ideal and this kind of problem would never show up in the sim.

Ok. I just need the switch from A to B and back be clean with no overlap

 

Ok. I just need the switch from A to B and back be clean with no overlap

My revised circuit in post #19 does that.

 

Well, if A to B is clean (acceptable) then I see no reason why B to A can't also be clean.

Just have to figure the reason why the two transitions are asymmetrical.

And I am assuming you are letting the timer run thru multiple cycles, because a single cycle would explain a lot because M1 gate doesn't charge until B is active.

 

Hmmmmm…. 404

No attachment is visible

 

Well, if A to B is clean (acceptable) then I see no reason why B to A can't also be clean.

Just have to figure the reason why the two transitions are asymmetrical.

And I am assuming you are letting the timer run thru multiple cycles, because a single cycle would explain a lot because M1 gate doesn't charge until B is active.

Totally agree.. I ran the sw circuit 30 minutes or more. Starting stoping. Always the same identical operation. Lean first change A to B. Both stay on for a short bit when B to A? Can’t use it on my project until the switch is a clean break from one load to the other…

 

Well, if A to B is clean (acceptable) then I see no reason why B to A can't also be clean.

The reason is, because the delay required for non-overlap is different for the two transitions (see below):
Note that Ck1 is delayed on its rise but not fall, and Ck2 is also delayed on its rise but not fall.
And the output rise is delayed, but the transition time is unaffected.
That's why I added the circuit which generates the rise delays needed to guarantee non-overlap on both sets of transitions.

 

Because the delay required for non-overlap is different from the two transitions (see below):
That's why I added the circuit to guarantee non-overlap.

View attachment 321536

Added Circuit? Did I miss an alteration?

 

Added Circuit? Did I miss an alteration?

Yes, as I've said, in post #19.

 

Added Circuit? Did I miss an alteration?

Yes, as I've said, in post #19.

I’ll breadboard it here in a few. Appreciate all the help and looking forward to trying it out.

 

I’ll breadboard it here in a few. Appreciate all the help and looking forward to trying it out.

You can adjust the values of R8 and/or C3 to change the value of the non-overlap time, if needed.

For your info, below are the pin designations for the CD4093 to help with your wiring:

 

You can adjust the values of R8 and/or C3 to change the value of the non-overlap time, if needed.

For your info, below are the pin designations for the CD4093 to help with your wiring:

View attachment 321558

On your new circuit you labeled pin4 of the 555 as Vdd not reset and looks not connected? Is that your intent?

 

You can adjust the values of R8 and/or C3 to change the value of the non-overlap time, if needed.

For your info, below are the pin designations for the CD4093 to help with your wiring:

View attachment 321558

On you circuit with 4093 you show pin 4 of 555 as Vdd and not connected. Is that your intent?

 

On you circuit with 4093 you show pin 4 of 555 as Vdd and not connected. Is that your intent?

Scratch that, lol

 

9v is a bench supply. The LEDs have current limiting resistors. Can you elaborate a bit on the alterations to Q1?

but what is the current limit set at? did you monitor voltage? what is the LED current? your comments suggested that brightness dropped after two clocks..

the Q1, M1 and M2 need to work like switches. if they do, everything is fine.
the challenge is if they enter linear mode. with Q1 and large value base resistor this is likely the case. using Schmidt triggers ensures steep edges and problem goes away. adding delay between transitions allows for some safety margins too.

 

You can adjust the values of R8 and/or C3 to change the value of the non-overlap time, if needed.

For your info, below are the pin designations for the CD4093 to help with your wiring:

View attachment 321558

Works fine with no overlap. I’ve played with the resistors/cap and see I can change speed. Is there a way I can get the A or B load to remain on longer than the other? I’d like A or B to be on half as long as the other?

 

I’ve played with the resistors/cap and see I can change speed.

That changes the non-overlap time, it has nothing to do with the speed.

Is there a way I can get the A or B load to remain on longer than the other?

The value of R2 on the 555 determines the on-time of B, and the value of R1 + R2 determines the on-time of A.