Hi all,
I was trying to simulate the schematic seen in the following video:

I don't understand why I can't get it to work.
Does anyone have any ideas?
Thanks

 

The initial condition is the problem. Try to use this ".tran 0.1 startup" (start external DC supply voltage at 0V this box must be checked )

 

The initial condition is the problem. Try to use this ".tran 0.1 startup" (start external DC supply voltage at 0V this box must be checked )

Thanks.
I've tried to play with the passives values and I obtained max 2kHz freq signal.
Do you think that using this circuit I can obtain a 70kHz signal?
Thanks

 

Try this version:

 

Very good!
what do you think is the reason for the distortion at low voltage?
Thanks

 

what do you think is the reason for the distortion at low voltage?

If you mean the sawtooth flat bottom, that's due to saturation delay (time to come out of saturation) in the two transistors that discharge the capacitor.
General purpose transistors can have a significant delay (often more than a microsecond).
If you change to switching transistors with low delay, such as a 2N2369 for Q1 and 2N5771 for Q3, that will largely disappear.
Switching transistors can often be recognized by their relatively low max Vceo ratings (here they are both 15V), but you need to look at their data sheets to determine that for certain.

 

If you mean the sawtooth flat bottom, that's due to saturation delay (time to come out of saturation) in the two transistors that discharge the capacitor.
General purpose transistors can have a significant delay (often more than a microsecond).

Thanks!
If I wanted the waveform to reach 0V I would have to use mosfets right?

 

If I wanted the waveform to reach 0V I would have to use mosfets right?

Not necessarily.
You would have to use a different circuit.
Most of the observed voltage above 0V (about 0.8V) is due to Q3's Vbe (base-emitter) voltage, not its saturation voltage.

Why do you want 0V?
How close to zero do you need?

Adding a transistor to help discharge the cap gets it down to a little over 100mV (below).

 

Why do you want 0V?
How close to zero do you need?

This circuit is for a friend of mine that asked me it as part of a class D amplifier.
could you explain to me what is the purpose of Q4?
Thanks

 

This circuit is for a friend of mine that asked me it as part of a class D amplifier.

So it's for the PWM modulator I assume.
For that, the sawtooth doesn't need to go to 0V, you can just offset the audio modulation signal DC value to the middle of the sawtooth that goes to the comparator to give a 50% duty-cycle with zero AC modulation signal, which is the usual design goal.

 

could you explain to me what is the purpose of Q4?

That is to pull the capacitor voltage down to near the Vce ON saturation voltage, which is lower than the base-emitter voltage.