Setting up ADC on PIC32MX534F064H

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Joined Jan 18, 2013

Would be very thankful if someone could help me out with this.

I am working on a small project which uses a PIC32MX534F064H MCU, I am trying to make the ADC read a voltage level on one of the Analog pins, but haven't been able to make it work.

My reference is the Datasheet for the MCU in question Datasheet.

I been trough the Datasheet multiple times but I am missing something and don't know what.

I have set up the ADC to Auto convert Mode and in the program code I am comparing the ADC1BUF0 against a value of (Int 500) to turn an LED on, this is just to verify that the ADC Setup is working, but so far no success.

Below is the code I'm loading in to the MCU:


#pragma config USERID = 0xFFFF          // Enter Hexadecimal value (Enter Hexadecimal value)
#pragma config FSRSSEL = PRIORITY_7     // SRS Select (SRS Priority 7)
#pragma config FCANIO = ON              // CAN I/O Pin Select (Default CAN I/O)
#pragma config FUSBIDIO = OFF           // USB USID Selection (Controlled by Port Function)
#pragma config FVBUSONIO = OFF          // USB VBUS ON Selection (Controlled by Port Function)

#pragma config FPLLIDIV = DIV_12        // PLL Input Divider (12x Divider)
#pragma config FPLLMUL = MUL_24         // PLL Multiplier (24x Multiplier)
#pragma config UPLLIDIV = DIV_12        // USB PLL Input Divider (12x Divider)
#pragma config UPLLEN = OFF             // USB PLL Enable (Disabled and Bypassed)
#pragma config FPLLODIV = DIV_256       // System PLL Output Clock Divider (PLL Divide by 256)

#pragma config FNOSC = PRI              // Oscillator Selection Bits (Primary Osc (XT,HS,EC))
#pragma config FSOSCEN = OFF            // Secondary Oscillator Enable (Disabled)
#pragma config IESO = OFF                // Internal/External Switch Over (Enabled)
#pragma config POSCMOD = EC             // Primary Oscillator Configuration (External clock mode)
#pragma config OSCIOFNC = OFF           // CLKO Output Signal Active on the OSCO Pin (Disabled)
#pragma config FPBDIV = DIV_8           // Peripheral Clock Divisor (Pb_Clk is Sys_Clk/8)
#pragma config FCKSM = CSDCMD           // Clock Switching and Monitor Selection (Clock Switch Disable, FSCM Disabled)
#pragma config WDTPS = PS1048576        // Watchdog Timer Postscaler (1:1048576)
#pragma config FWDTEN = OFF             // Watchdog Timer Enable (WDT Disabled (SWDTEN Bit Controls))

#pragma config DEBUG = OFF              // Background Debugger Enable (Debugger is disabled)
#pragma config ICESEL = ICS_PGx2        // ICE/ICD Comm Channel Select (ICE EMUC2/EMUD2 pins shared with PGC2/PGD2)
#pragma config PWP = OFF                // Program Flash Write Protect (Disable)
#pragma config BWP = OFF                // Boot Flash Write Protect bit (Protection Disabled)
#pragma config CP = OFF                 // Code Protect (Protection Disabled)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

#include <xc.h>

#include <stdio.h>
#include <stdlib.h>

int main(int argc, char** argv) {
    // ADC Settings:
    TRISB = 0x3000; //0011000000000000;
    AD1CHS = 0xD0000;  //00000000000011010000000000000000;
    AD1CON1 = 0xE4; //0000000011100100
    AD1CON2 = 0x0; //0000000000000000
    AD1CON3 = 0x8200; //1000001000000000
    AD1CON1 = 0x80E4; //1000000011100100
    //LED Settings
    TRISF = 0;  //Data Direction Register (Tri State, Switch) "0 for Output" "1 For Input"

    while (1) 
        if (ADC1BUF0 >= 50) {
            LATF = 15;  //Latch Register
        else {
            LATF = 0;  //Latch Register

    return (EXIT_SUCCESS);


Thanks in Advance



Joined Aug 27, 2009
I didn't look very closely at the code but you must check to see if at least one conversion was completed before checking ADC1BUF0 for valid data.

17.5.6 DONE Bit Operation The DONE bit (AD1CON1<0>) is set when a conversion sequence is complete. In Manual mode, the DONE bit is persistent. It remains set until it is cleared by software. The DONE bit can be polled to determine when the conversion has completed. In all automatic sample modes (ASAM bit = 1), the DONE bit is not persistent. It is set at the end of a conversion sequence and cleared by hardware when the next acquisition is started. Polling the DONE bit is not recommended when operating the ADC in automatic modes. The AD1IF flag bit (IFS1<1>) is latched after a conversion sequence is completed and can therefore be polled. Figure 17-5 shows the ADC configuring for Alternate Sampling mode. Figure 17-6 shows the ADC configuration for Scan mode. Figure 17-7 shows the ADC configuration for a combination of Alternate Sampling mode and Scan mode.

Example 17-5: Converting 1 Channel, Auto-Sample Start, Conversion Trigger Based Conversion Start Code
Code fragment
while (!IFS1 & 0x0002){}; // conversion done? 
ADCValue = ADC1BUF0; // yes then get first ADC value 
IFS1CLR = 0x0002; // clear ADIF