Sending to more shift rigisters

Thread Starter

FroceMaster

Joined Jan 28, 2012
662
Hi.
Maybe silly question.
I have this setup with 4 * tpic6b595 in series
if i send like this code.

C:
 #define DATA_pin PORTBbits.RB2
#define LATCH_pin  PORTAbits.RA5
#define CLCOK_pin  PORTBbits.RB1

void clock_signal(void){
   CLCOK_pin = 1;
    __delay_us(500);
   CLCOK_pin = 0;
    __delay_us(500);
}
void latch_enable(void)
   {
    LATCH_pin = 1;
    __delay_us(500);
    LATCH_pin = 0;
    }
void send_data(unsigned int data_out)
{
    int i;
    for (i=0 ; i<8 ; i++)
    {
        DATA_pin = (data_out >> i) & (0x01);
        clock_signal();
    }
    latch_enable(); // Data finally submitted
}
void main (void)
{
//init allthing, that part is ok.
   
    while (1)
    {
        send_data(0b00000011);
        send_data(0b11000000);
        send_data(0b00110000);
        send_data(0b00001100);
       
    }
   
    }
Can i send 4 parts of data right after each other, or do the LATCH need to come to last ?
Meaning, will the update of shift register be notitsable ?
 
Last edited:

Papabravo

Joined Feb 24, 2006
15,481
I'm not sure exactly what you are asking, but I don't think you have to latch the shift register data after each byte is sent. If it is wired the way it should be you can shift the combined registers 32 times and then latch all 32 bits at one time. A schematic diagram would help us confirm this.
 

trebla

Joined Jun 29, 2019
268
According to tpic6b595 datasheet the data reads in during clock signal is changing low to high. This means you must make CLCOK_pin low before changing DATA_pin and raise back high after canging the DATA_pin.
Same for LATCH_pin - before starting transmission make it low and after transmission end allow outputs again.

EDIT: LATCH_pin signal is inverted, active state is low. Before starting a new transmission session is better to reset registers ( reset is low also)
 
Last edited:

Thread Starter

FroceMaster

Joined Jan 28, 2012
662
I'm not sure exactly what you are asking, but I don't think you have to latch the shift register data after each byte is sent. If it is wired the way it should be you can shift the combined registers 32 times and then latch all 32 bits at one time. A schematic diagram would help us confirm this.
Ok, yes it's wired in serie, so i will move the "latch_enable" to all is send.
if i use the Latch after each 8 bit, the digit will be updatet with the wrong data, but if shiftet so fast, i dont know if we can see it.
ex if all digits is clear and i want to write 1234 into them, and lets say i send from right to left the "1" will first be in digits 4 place, and the digits 3 ect, but it will shift so fast that nowone will notice i think.
 

ericgibbs

Joined Jan 29, 2010
12,217
hi,
You use the G, Enb pin to set the Output pins to the states of the individual cell/bits.
ie; shift in new data with the Enb Off, when all bits shifted, set Enb On.

Also note the RCK, output Register load.

E
 

Attachments

Papabravo

Joined Feb 24, 2006
15,481
Ok, yes it's wired in serie, so i will move the "latch_enable" to all is send.
if i use the Latch after each 8 bit, the digit will be updatet with the wrong data, but if shiftet so fast, i dont know if we can see it.
ex if all digits is clear and i want to write 1234 into them, and lets say i send from right to left the "1" will first be in digits 4 place, and the digits 3 ect, but it will shift so fast that nowone will notice i think.
I don't think you understand. Each 595 has a shift register and a latch. You cannot see the outputs of the shift register they are internal to the part. The ONLY thing you can see externally is the output of the latch. The procedure you need to use is:
  1. Shift 32 bits into the shift register. At this time those data are not visible externally. what is visible is the previous data that was there in the latch.
  2. Send one latch enable signal to all four parts, to simultaneously transfer the data from the shift register to the latch, and thus make the data visible externally.
  3. When the latch enable signal is removed, the latch will maintain the data in it's present state until there is new data in the shift register and a subsequent latch enable is active.
 

Thread Starter

FroceMaster

Joined Jan 28, 2012
662
I works fine with one 595, i just need to be sure i should shift all 32 bit out, and then LATCH, :)
Will return if problems,

#
ericgibbs
G pin number 9, i use to dimmer the LED, with a PWM signal at 125 hz. Works great.
Pin 3 is data in.
Pin 12 is Latch.
Pin 13 is CLOCK.
Pin 8 is by 10k ohm to +5v.
Pin18 is DATA out to next 595
.
Rgds
 
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