A lot probably depends on how many errors you can put up with. I've been involved with designing industrial control equipment for quit a few years. You can be sure that if I2C was reliable over significant lengths of cable, it would be in wide use. As it is not, that can be taken as a good indication. By all means have a go. It may work well enough for you. But don't be surprised if you spend quite a time mucking around for nothing. With all the rigmarole you are proposing to make it work, a separate processor on each end of an RS485 link to keep th I2C local sounds like a way easier approach to me.

 

Hi TeeKay6,

Thanks a lot for your help! I'm terrible at understanding datasheets, and it's something I certainly will work on. Its mainly why I trust people like yourself and ebeowulf17 on this forum to help me out.

As for the speed of the data transfer, TeeKay6, 50us/bit, is that 20kbps? I think the VL53L0X operates at one speed, 100kbps. I will definitely try just the twisted pair approach. I saw a guy on youtube send ground as the paired wire in each twisted pair to get a longer range. but the cable was coiled up and i thought that coiling up a cat5e cable increases its signal transmission aswell, so i didnt know how much to believe in his theory.

I have thought about all your super helpful advice and come up with a new schematic. I tried LT spice and couln't figure out how to run the simulation, but I'll keep learning that too and figure it out. Im sure its something easy. I thought for now, I'd show you what ive done. I already have some NAND gates in my arsenal so, I'll continue to use them, plus, I think I've figured out a way to eliminate all external mosfets from the design.

 

FYI, 50μs/bit is 20kbs

 

Hi TeeKay6,

Thanks a lot for your help! I'm terrible at understanding datasheets, and it's something I certainly will work on. Its mainly why I trust people like yourself and ebeowulf17 on this forum to help me out.

As for the speed of the data transfer, TeeKay6, 50us/bit, is that 20kbps? I think the VL53L0X operates at one speed, 100kbps. I will definitely try just the twisted pair approach. I saw a guy on youtube send ground as the paired wire in each twisted pair to get a longer range. but the cable was coiled up and i thought that coiling up a cat5e cable increases its signal transmission aswell, so i didnt know how much to believe in his theory.

I have thought about all your super helpful advice and come up with a new schematic. I tried LT spice and couln't figure out how to run the simulation, but I'll keep learning that too and figure it out. Im sure its something easy. I thought for now, I'd show you what ive done. I already have some NAND gates in my arsenal so, I'll continue to use them, plus, I think I've figured out a way to eliminate all external mosfets from the design.View attachment 181577

@gkeep
Re: LM339 version schematic, Some initial observations:
1. A pullup is missing for the Slave SCL signal.
2. The Slave SCL signal is inverted from the Master SCL signal.
3. Why did you choose R1 & R6 = 20K, but R3 = 1K?
4. The Slave SDA signal is inverted from the Master SDA signal.
5. You cannot safely use a comparator (or an op-amp configured as comparator) if there is a case when both comparator inputs are high or both inputs are low. Under that condition the comparator output is indeterminate (could be high or low, depending on the specific physical device). After you fix the inversion noted in 4. above, you must make sure neither indeterminate case ever arises when you expect valid data to be on the Slave SDA.
6. With so much logic between the Master and Slave, I worry that you may encounter race conditions (i.e. a signal is still changing when it is expected to be stable). Such problems will be worse as higher speeds are used. Restated, each logic gate and comparator (or op-amp) has a delay between when its input changes and its output changes; these delays vary between different devices and even between multiple gates within one package. Race problems can be very difficult to diagnose!
7. You must verify that the LM339 devices you use (i.e. the specific brand) tolerate input voltages up to the power supply voltage without phase inversion. That is, you must verify that the correct comparator logic occurs for any value of inputs between ground and Vcc--since that is the presumed output range of the NAND gates you will use.

Search AAC for other I2C projects/forum entries such as "I2C long distance", "I2C extend". There is a lot of info available (unfortunately, also a lot of reading).

Frankly, I suggest that learning to use simulator software (e.g. LTspice from Analog Devices) ought to be higher priority for you than making guesses at this circuit. A simulation taking 3 seconds to run could easily save you 3 weeks of effort.

Coiling Cat5e (or other Cat) cable loosely will have only a very minor effect on performance.

 

Just an FYI -- we've done a few articles on I2C:

https://www.allaboutcircuits.com/te...esign-mathematics-capacitance-and-resistance/

https://www.allaboutcircuits.com/technical-articles/the-i2c-bus-hardware-implementation-details/

etc...

In short -- the inherent capacitance of 7 meters of wire will force the bus speed to be very, very low, even if you use low-value pull-up resistors. My recommendation is to choose a different protocol.

 

Just an FYI -- we've done a few articles on I2C:

https://www.allaboutcircuits.com/te...esign-mathematics-capacitance-and-resistance/

https://www.allaboutcircuits.com/technical-articles/the-i2c-bus-hardware-implementation-details/

etc...

In short -- the inherent capacitance of 7 meters of wire will force the bus speed to be very, very low, even if you use low-value pull-up resistors. My recommendation is to choose a different protocol.

But wont a differential signal over a properly terminated twisted pair, reduce capacitance by orders of magnitude? I thought that is what this whole thing was about.

 

But wont a differential signal over a properly terminated twisted pair, reduce capacitance by orders of magnitude? I thought that is what this whole thing was about.

So there's a few things to unpack from that statement.

First, unrelated to your statement -- what you propose in #42 is no longer I²C -- it's something you've invented that doesn't have a name -- so you've got that going for you. "I2C Design Guides" like the one I offered in the previous message aren't directly applicable when you're not technically using I2C. So my recommendations may/may not apply.

Won't a differential signal over a properly terminated twisted pair, reduce capacitance by orders of magnitude?

Capacitance is a property of any two conductors, based on their separation, surrounding dielectric, and electric field. But I would actually expect capacitance to increase in a differential pair of a Cat 5e/6 cable bundle when compared to two similarly-sized conductors in a parallel configuration (24 AWG). Here's why -- capacitance is inversely proportional to the distance between the conductors -- and the conductors in a Cat5e/6 cable have less insulation on each individual conductor, so the conductors are closer together. In a standard ribbon-cable configuration, the insulation tends to be thicker on each individual strand -- this is necessary to protect the conductors of the ribbon-cable because they lack the external jacketing that Cat 5e/6 has. I pulled a couple of data sheets -- certainly not an exhaustive sample. But it looks like the jacket thickness of parallel conductor cable is 1.8mm, and the jacket thickness of ethernet twisted pair is 0.010 inches (0.254 mm).

http://www.tensility.com/pdffiles/30-00003.pdf

http://www.alphawire.com/Home/Produ.../High-Low-Temperature-Cable/2831_2?device=pdf

Something else I should ask (my apologies if it was answered on a previous page) -- but what is the calculated voltage drop over the round-trip distance? I assume on the left side of your circuit you've got 3.3 V -- what is it by the time it reaches the right side of your circuit? And then once it returns back to the left? That will affect your logic levels as well.

 

So there's a few things to unpack from that statement.

First, unrelated to your statement -- what you propose in #42 is no longer I²C -- it's something you've invented that doesn't have a name -- so you've got that going for you. "I2C Design Guides" like the one I offered in the previous message aren't directly applicable when you're not technically using I2C. So my recommendations may/may not apply.


@gkeep
As @Mark Hughes said, the effect of twisted wires vs untwisted wires is to increase the capacitance between the two wires (they are held in close, though insulated, contact and more wire length is needed for twisting). The advantage of a twisted pair (vs untwisted) is that it provides improved immunity to nearby interfering signals due to magnetic and electrostatic coupling; that is, twisting improves the rejection of common-mode noise. Viewing a CAT5e twisted pair as a transmission line would show the benefit of terminating the pair in its "characteristic impedance"; one benefit is that less ringing will occur at the far end of the driven pair and less energy will be reflected back to the driver. (Search "transmission line" for more info.) In your case, the 100Ω termination (for Cat5e) would place a 100Ω resistor between the output of one NAND gate (e.g. U1) and the output of the succeeding NAND gate (U2). I believe that the NAND gates would likely be unhappy with that load. In short, the purpose and result of twisting is not to reduce capacitance.

Capacitance is a property of any two conductors, based on their separation, surrounding dielectric, and electric field. But I would actually expect capacitance to increase in a differential pair of a Cat 5e/6 cable bundle when compared to two similarly-sized conductors in a parallel configuration (24 AWG). Here's why -- capacitance is inversely proportional to the distance between the conductors -- and the conductors in a Cat5e/6 cable have less insulation on each individual conductor, so the conductors are closer together. In a standard ribbon-cable configuration, the insulation tends to be thicker on each individual strand -- this is necessary to protect the conductors of the ribbon-cable because they lack the external jacketing that Cat 5e/6 has. I pulled a couple of data sheets -- certainly not an exhaustive sample. But it looks like the jacket thickness of parallel conductor cable is 1.8mm, and the jacket thickness of ethernet twisted pair is 0.010 inches (0.254 mm).

http://www.tensility.com/pdffiles/30-00003.pdf

http://www.alphawire.com/Home/Produ.../High-Low-Temperature-Cable/2831_2?device=pdf

But wont a differential signal over a properly terminated twisted pair, reduce capacitance by orders of magnitude? I thought that is what this whole thing was about.

Something else I should ask (my apologies if it was answered on a previous page) -- but what is the calculated voltage drop over the round-trip distance? I assume on the left side of your circuit you've got 3.3 V -- what is it by the time it reaches the right side of your circuit? And then once it returns back to the left? That will affect your logic levels as well.

 

As I indicated in post 12, I have successfully connected my Feather HUZZAH with ESP8266 WiFi to a BME 680 I2C device over 50ft (15 meters) using a 6 conductor phone line extension cord. Seems to be 'talking' with no issues so far.

I connected 2 devices per the http://www.ti.com/lit/ds/symlink/p82b715.pdf document.

 

Thanks, I've learned a lot from you guys. I've been playing around with LT Spice trying hours trying to find schematic that works with next to no luck. I found that even though I've mirrored the master and slave differential and low latching avoidance logic, I'm getting different results in both LT Spice and on my lab bench, for the slave and master high/low states of the SDA line. Which is weird. I tried BUZZ11N mosfets.

I feel like giving up on this. I wouldn't have thought it would be so difficult to send i2c differentially, especially considering they shouldn't talk unless the master sends a request. Where I am having issue is sending the output from one logic gate to drive both the gate of a mosfet as well as another input of another logic gate. The mosfets becomes slightly conductive when it shouldn't and a high out of the first gate no longer switches fully on the mosfet. I think I have a solution for that and ill keep you posted.

markcf,

Thanks i will certainly look at your option. I was wondering, do you need to terminate your twisted pairs for your 15 meter transmission or is it just wired in as per usual? Also are you just running 1 master and 1 slave? Also, which lines are sharing the twisted pairs?

Cheers,

 

EDIT: I show the SDA pull ups connected to 0v0. They should be connected to 3v3, the same as the SCL pull ups.

Here is my circuit.

http://www.ti.com/lit/ds/symlink/p82b715.pdf

I just used 6 conductor 'flat' phone line and probably could have used 4 conductor. 6 conductor 50 ft roll was all that Good Will had tho.
Wire roll came with the phone connector jacks and I plugged them into a CAT5 receptacle.

Connected 0v0 and 3v3 and ran SDA and SCL on the other 2.

I suspect that if you extended run to 33m (100ft), you might have to take more care.

 

Trying to make IIC fit where it is not intended will probably be a lot harder than just using RS485 (or even RS232).

 

Thanks, I've learned a lot from you guys. I've been playing around with LT Spice trying hours trying to find schematic that works with next to no luck. I found that even though I've mirrored the master and slave differential and low latching avoidance logic, I'm getting different results in both LT Spice and on my lab bench, for the slave and master high/low states of the SDA line. Which is weird. I tried BUZZ11N mosfets.

I feel like giving up on this. I wouldn't have thought it would be so difficult to send i2c differentially, especially considering they shouldn't talk unless the master sends a request. Where I am having issue is sending the output from one logic gate to drive both the gate of a mosfet as well as another input of another logic gate. The mosfets becomes slightly conductive when it shouldn't and a high out of the first gate no longer switches fully on the mosfet. I think I have a solution for that and ill keep you posted.

markcf,

Thanks i will certainly look at your option. I was wondering, do you need to terminate your twisted pairs for your 15 meter transmission or is it just wired in as per usual? Also are you just running 1 master and 1 slave? Also, which lines are sharing the twisted pairs?

Cheers,

@gkeep
Congratulations on starting to learn & use spice software (LTspice). Although you may not have found the answers you wanted for this project, you now have a new tool to help with future projects. You can upload LTspice's project files (.asc) to help others help you. Good luck!

 

I think I'm making some headway, and ill keep you posted. I'm seeing three limitation in LT Spice that the logic gates can only output 1 volt. I'll let you know how I go, I'm busy with some other projects but over the next few days I'll make the decision whether to continue with this.

 

I think I'm making some headway, and ill keep you posted. I'm seeing three limitation in LT Spice that the logic gates can only output 1 volt. I'll let you know how I go, I'm busy with some other projects but over the next few days I'll make the decision whether to continue with this.

@gkeep
The default logic gates are truly "logic only" and output a symbolic 0 or 1. However, there are many libraries of logic and other devices for specific families of real devices that can be downloaded and used in LTspice, most of them for free. Try searching AAC and the Web for "LTspice library". Also, the forums at Analog Devices and StackExchange.com.

 

I think I'm making some headway, and ill keep you posted. I'm seeing three limitation in LT Spice that the logic gates can only output 1 volt. I'll let you know how I go, I'm busy with some other projects but over the next few days I'll make the decision whether to continue with this.

You can make the logic gate voltages whatever you want with vlow and vhigh commands. You can see the commands on my schematics (post 34, I think.) If you right click on the logic gate, you can edit its parameters. I forget which line you put those parameters in, but if you open my .asc file you can see what I did.

The real problem with using these logic gates for simulation is the lack of real world timing constraints and parasitics (capacitance, inductance, etc.) You can set the voltage levels they operate at, but they'll still behave as ideal gates, not realistic ones. The difference between the two is significant when attempting high speed communication!

 

Trying to make IIC fit where it is not intended will probably be a lot harder than just using RS485 (or even RS232).

I suspect that is why TI developed this chip.

 

I solved this problem before a couple of years ago. They make I2C bus extenders. I used the P82B715 for my project. It ran the full speed of the I2C bus. 100 or 400 kbps.

I have attached the first page of the project showing the ICs used. The schematic also includes an I2C multiplexer if you want to expand the number of devices. I had 40 sensors that only talked I2C and they had to be mounted inside a chamber and required a long cable.