Self-clocking D flip flop

Thread Starter

pdumais

Joined Mar 4, 2020
7
Hi,

I'm trying to build an edge detector using a flip flop. Basically, I want a relay to activate for about 1s an input signal rises and when it falls.
I'm having a hard time implementing the 1s delay using an RC circuit attached from the output of the flip-flop and fed back into its own clock pin..

Something like this: http://tinyurl.com/ttxztto
the circuit works and does exactly what I need in the simulation (other than I have to change the cap/resistor values to get 1s). But it works differently in real life. Because I have to add a pull-down resistor on the clk pin and that messes up the RC circuit I think because that creates a voltage divider. I don't know enough at that point... Can someone point me in the right direction?

Thanks.
 

WBahn

Joined Mar 31, 2012
25,750
You goals aren't quite clear. Is the switch going to be a momentary connection or is it going to be static? What do you want to have happen if they close the switch and then open it 0.5 seconds later?

When the switch is open then the D input and the input to the NAND gate are floating. This is generally a bad thing. If you want reliable operation you will need a pulldown on the D input. If you are using TTL parts, then this is essential as those parts have an intrinsic weak pullup behavior on unconnected inputs.

Your clock signal is going to be a slow-changing signal and thus the DFF may trigger many times as it passes through the critical region. Buffer the signal with two inverters in series to sharpen it up. Preferably, use parts that have Schmidt trigger inputs.
 

MrChips

Joined Oct 2, 2009
21,087
You need to separate the two functions:

1) You need a circuit that responds to both rising and falling transitions.

2) You need a circuit that generates a 1-second pulse.
 

Thread Starter

pdumais

Joined Mar 4, 2020
7
You goals aren't quite clear. Is the switch going to be a momentary connection or is it going to be static? What do you want to have happen if they close the switch and then open it 0.5 seconds later?

When the switch is open then the D input and the input to the NAND gate are floating. This is generally a bad thing. If you want reliable operation you will need a pulldown on the D input. If you are using TTL parts, then this is essential as those parts have an intrinsic weak pullup behavior on unconnected inputs.

Your clock signal is going to be a slow-changing signal and thus the DFF may trigger many times as it passes through the critical region. Buffer the signal with two inverters in series to sharpen it up. Preferably, use parts that have Schmidt trigger inputs.
The switch is going to be static. It's actually a digital output of a microcontroller. I understand the problem about close/open within 0.5s but that is not a concern for me at this point.

I agree with you on the pulldown for D, I've done this on my circuit board. I tried to make the example simple, but here is a more realistic one: http://tinyurl.com/v3tqlnp
 

Thread Starter

pdumais

Joined Mar 4, 2020
7
It works in the simulation but I don't think it would work for real because of the pull-down resistor on the clock pin.

I think that my problem is that I have the rc output going to the clk pin while that pin is tied to ground thru a resistor. This effectively makes a voltage divider no? and the voltage entering the clk pin is two low.
 

WBahn

Joined Mar 31, 2012
25,750
It works in the simulation but I don't think it would work for real because of the pull-down resistor on the clock pin.

I think that my problem is that I have the rc output going to the clk pin while that pin is tied to ground thru a resistor. This effectively makes a voltage divider no? and the voltage entering the clk pin is two low.
If you use a pulldown resistor then it's value would need to be large enough so that the voltage-divider action isn't enough to prevent it from reaching a valid logic HI. But you probably won't need a pulldown on it if you take steps to sharpen it up.
 

crutschow

Joined Mar 14, 2008
24,942
Below is the LTspice simulation of CD4093 Schmitt-trigger NAND gates configured as an XOR to generate a 1 second pulse on both the leading and trailing edges of the input pulse:
The blue trace is the input pulse, and the yellow trace is the relay coil current.

1583337996660.png
 

Alec_t

Joined Sep 17, 2013
11,276
You could do this with an XOR gate and R/C.
That simple circuit in the link does however mean that the input signal high period and signal low periiod must each be a lot longer than 1 sec, if both edges of the signal have to produce a consistent 1 sec output pulse width.
Here's a somewhat more complex alternative which avoids that limitation :-
1sec-pulser.png
 

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Thread Starter

pdumais

Joined Mar 4, 2020
7
Thank you crutschow. That seems like a solution that will work but I don't have any NANDs on hand right so I think I'll try the XOR way. It doesn't matter if the input needs to stay on for a while.

I tried to simulate this but I can't figure out how to get falling edge detection to work: http://tinyurl.com/s3mz7qm
I added a resistor to ground to discharge the capacitor when the swtich is off but for some reason, the diode in the simulation does not seem to work. Also, it's taking too much time to discharge ...
 

djsfantasi

Joined Apr 11, 2010
6,421
Thank you crutschow. That seems like a solution that will work but I don't have any NANDs on hand right so I think I'll try the XOR way. It doesn't matter if the input needs to stay on for a while.

I tried to simulate this but I can't figure out how to get falling edge detection to work: http://tinyurl.com/s3mz7qm
I added a resistor to ground to discharge the capacitor when the swtich is off but for some reason, the diode in the simulation does not seem to work. Also, it's taking too much time to discharge ...
The NANDs that crutschow used are wired to act as one XOR gate. He used NAND gates, because the circuit also needs a NAND gate.

Google “XOR with NAND gates” to see how he did this.
 

djsfantasi

Joined Apr 11, 2010
6,421
Actually, I used Schmitt-trigger NAND gates to generate the XOR function, to avoid any oscillation of the output during the slow input transition caused by the RC delay, which a standard XOR may cause.
Yep, I didn’t notice that. But why wouldn’t a Schmitt-trigger XOR gate be all that is required? An SN74HCS86 for example?
 
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