Sawtooth generator capacitor discharge time

Thread Starter

Jack Tranckle

Joined Jan 20, 2016
73
I am wanting to desing a new DCO. I am trying to understand/calculate how long the capacitor C9 will take to discharge to 0V . The integrator produces a negative ramp up to a maximum of around -4.5V, a pulse width then switches the FET (j201), which discharges the C9. However the length that it takes is important, as the pulse width must have the same time. thank you in advance

According to the multisim simulation, the capacitor discharges in 3.4us. So I am looking for a similar calculated value


cccccccccc.png
 
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danadak

Joined Mar 10, 2018
4,057
You start by defining what the criteria for reset is in terms
of cap voltage. then using -

upload_2018-5-4_7-19-46.png

Where R = Rdson of JFET, solve for t. That will give you
necessary PW.

This is not exact solution as the input R to the integrator will contribute error,
but as a first order approximation this method should work fine.

Regards, Dana.

Regards, Dana.
 

Thread Starter

Jack Tranckle

Joined Jan 20, 2016
73
You start by defining what the criteria for reset is in terms
of cap voltage. then using -

View attachment 151878

Where R = Rdson of JFET, solve for t. That will give you
necessary PW.

This is not exact solution as the input R to the integrator will contribute error,
but as a first order approximation this method should work fine.

Regards, Dana.

Regards, Dana.
Sorry I am a bit confused by what you mean, are you referring to this equation?

Capture.PNG

if so, I believe solving for t gives:

Capture.PNG

Vc I am guessing is the 4.5 Volts (value before discharged ), but what is V0? According to the datasheet. Rds(on) is 30ohms.
 

danadak

Joined Mar 10, 2018
4,057
V0 is initial V of capacitor before discharge. Vc is the instantaneous value of
the capacitor at a point in time as its discharging.

Regards, Dana.
 

Thread Starter

Jack Tranckle

Joined Jan 20, 2016
73
Im not really sure what I am missing then, plugging into the equation gives a very different value. I used 0.01 to represent the capacitor fully discharged.

t = (ln(0.01) - ln (4.5)) / (30ohms) X (1nF) = -203621 s ! way too big

I forgot to add before that when i simulate it, the capacitor discarges in about 3.4us.

Am i wrong in thing that the capacitor discharge time can just be calculated from t = RC? where 5t will be almost fully discharged ?

RC = (30ohm) (1nF) = 30ns
5RC = 150ns = 0.15 us

this is closer to the simulated value i guess
 
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crutschow

Joined Mar 14, 2008
25,133
The time it takes the integrator to return to zero is determined by the step-function response time of the U5-2 op amp as well as how fast C9 is discharged.
 

Thread Starter

Jack Tranckle

Joined Jan 20, 2016
73
The time it takes the integrator to return to zero is determined by the step-function response time of the U5-2 op amp as well as how fast C9 is discharged.
The slew rate is 13V/us, Im guessing this determines the step response? What calculation can I use to determine the time taken for the intergrator to reset crutschow? I really getting confused with this :)
 

danadak

Joined Mar 10, 2018
4,057
All depends on C. If C and Rdson very large then slew rate is irrelevant as the
rate of change is << Slew Rate (SR) limiting.

If they are small, yours is, then a sim would be relevant, or simply calc the rate of
change until it drops below SR limit, save that time calced, then use exponential
decay for the rest of the cycle. Then add the two times.

Basically the reset cycle slews to the point rate of change no longer SR limited,
then decays exponentially the rest of the way.

Or easy way, do a spice sim to check it out. Do this because its complicated,
the JFET is rapidly (relatively speaking) discharging the cap, while internally
the OpAmp is trying to get its comp cap charge changed in a virtually seperate
response until the amp falls below SR limiting.

The OpAmp is 13V / uS = 13 mV / nS.

Regards, Dana.
 
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crutschow

Joined Mar 14, 2008
25,133
Slewing 4.5V with a 13V/μs slew-rate takes 2.9μs, close to the 3.4μs in the simulation, so the simulation time appears to be mostly due to the opamp slew rate.
Thus a faster discharge response time will likely require a faster opamp.

Edit: Oops, I calculated that incorrectly. :oops:
It should be 4.5/13e6 = 0.35μs.
So the opamp slew rate is not a large part of the reset time.
 
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Hymie

Joined Mar 30, 2018
837
As crutschow says - a faster discharge response time will likely require a faster op-amp.

However if the limiting factor becomes the time taken by fet J102 to discharge the capacitor C9 – then by decreasing the capacitor value by a factor of 10 and increasing the value of resistor R8 by the same factor will keep the output waveform otherwise the same.

Note: by convention, transistors are identified by the prefix ‘Q’ and not ‘J’.
 

danadak

Joined Mar 10, 2018
4,057
Here is a sim where I started with C at 9V as initial condition.
You can see both slewing then control loop drops below
slew rate and exponentially decays to final value.

upload_2018-5-4_17-6-12.png

Regards, Dana.
 

crutschow

Joined Mar 14, 2008
25,133
Do you want a faster reset time or are you just interested in knowing how to calculate that time?

See my correction in post #11.
 
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Thread Starter

Jack Tranckle

Joined Jan 20, 2016
73
Do you want a faster reset time or are you just interested in knowing how to calculate that time?

See my correction in post #11.
Sorry I wasnt very clear, I am just interested in knowing how to calculate the time for the capacitor to discharge. I have a new project idea lined up and am just making sure I have a clear idea of the calculation. Thank you your post 11 was helpful, however I am trying to understand how to calculate an estimation for the time taken for the capacitor to discharge. It should be something around 4 - 5us.
 
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Thread Starter

Jack Tranckle

Joined Jan 20, 2016
73
Here is a sim where I started with C at 9V as initial condition.
You can see both slewing then control loop drops below
slew rate and exponentially decays to final value.

View attachment 151923

Regards, Dana.
Here is a sim where I started with C at 9V as initial condition.
You can see both slewing then control loop drops below
slew rate and exponentially decays to final value.

View attachment 151923

Oh wow thats incredible, so from what I can tell, the capacitor starts discharging at 100n, the slew rate effects it until 180n. What do you mean by the control loop? Id really like to try this simulation at the 4.5V maximum voltage of my design. Could you send the file attachment of by any chance or show it at 4.5? thanks ! :)

Regards, Dana.
 
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Thread Starter

Jack Tranckle

Joined Jan 20, 2016
73
I made some changes, mainly looking at plot x axis.

This is ADIsimPE from analog devices.

Sim attached.

Regards, Dana.
Thank you very much, it seems like an interesting bit of software! How did you start the initial condition of the capacitor charged? I am getting a triangle like form, I am wanting to just show the same results fro with the capacitor discharging from 4.5V, is this possible ?
 
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