Hi all, as an almost newbie on Synth DIY (I've did lot of little things in the past but I'm trying to diving conceptually into the deep level design details) I'm trying to grasp the basic concepts in a Sawtooth Core VCO design.
Here's one of the wonderful lectures by prof. Aaron Lanterman about this topic.

Since I'm trying to simulate the behavior of this circuit i tried a quick simulation with Falstad ( https://www.falstad.com/circuit/ ) but I can't make the JFET to discharge the capacitor at virtual ground when the reference 5V is reached. If i substitute the JFET with a manual plain switch I can discharge the capacitor and get and "hand-made" sawtooth. What am i doing wrong with the JFET?
I've attached the Falstad code as txt file and can be loaded in the Falstad online applet.

Thanks in advance

 

You are missing hysteresis -something to keep the FET on until the capacitor has discarged to where you want it. Instead you can put a monostable in series with the gate pulse (or even a pulse stretcher) to assure the FET stays on long enough for satisfactory discharge.