Hi,
I have written a Verilog code to transfer data from FPGA to my PC. I dont know much about serial communication. But in RealTerm, after I have set the baud rate, stop bits, parity bits etc...I get only one data repeated continuously. I dont know whats the issue. The verilog code snippet for sending data to PC is shared below. Whener I run, I only keep getting AB AB AB AB ... in my terminal. Also, when I put TxD_data <= TxD_data + 1; I keep getting random data which is not as expected. I dont know how to receive data correctly.
I have written a Verilog code to transfer data from FPGA to my PC. I dont know much about serial communication. But in RealTerm, after I have set the baud rate, stop bits, parity bits etc...I get only one data repeated continuously. I dont know whats the issue. The verilog code snippet for sending data to PC is shared below. Whener I run, I only keep getting AB AB AB AB ... in my terminal. Also, when I put TxD_data <= TxD_data + 1; I keep getting random data which is not as expected. I dont know how to receive data correctly.
- module tb_tx_serial(input clk, output TxD);
- // Inputs
- reg TxD_start;
- reg [7:0] TxD_data=0;
- reg [2:0] count=0;
- // Outputs
- //wire TxD;
- wire TxD_busy;
- // Instantiate the Unit Under Test (UUT)
- async_transmitter uut (
- .clk(clk),
- .TxD_start(TxD_start),
- .TxD_data(TxD_data),
- .TxD(TxD),
- .TxD_busy(TxD_busy)
- );
- //assign TxD_start = 1'b1;
- always@(posedge clk)
- begin
- TxD_start <= 1'b1;
- if(count < 4) begin
- TxD_data <= 8'hAB; end
- else begin
- TxD_data <= 8'hCD; end
- end
- always@(posedge clk)
- begin
- count <= count + 1;
- end
- endmodule