RS232 Serial communication from FPGA to PC

Discussion in 'Embedded Systems and Microcontrollers' started by Shankdeep Mukerji, Dec 22, 2015.

  1. Shankdeep Mukerji

    Thread Starter New Member

    Dec 22, 2015

    I have written a Verilog code to transfer data from FPGA to my PC. I dont know much about serial communication. But in RealTerm, after I have set the baud rate, stop bits, parity bits etc...I get only one data repeated continuously. I dont know whats the issue. The verilog code snippet for sending data to PC is shared below. Whener I run, I only keep getting AB AB AB AB ... in my terminal. Also, when I put TxD_data <= TxD_data + 1; I keep getting random data which is not as expected. I dont know how to receive data correctly.

    1. module tb_tx_serial(input clk, output TxD);

    2. // Inputs
    3. reg TxD_start;
    4. reg [7:0] TxD_data=0;
    5. reg [2:0] count=0;

    6. // Outputs
    7. //wire TxD;
    8. wire TxD_busy;

    9. // Instantiate the Unit Under Test (UUT)
    10. async_transmitter uut (
    11. .clk(clk),
    12. .TxD_start(TxD_start),
    13. .TxD_data(TxD_data),
    14. .TxD(TxD),
    15. .TxD_busy(TxD_busy)
    16. );

    17. //assign TxD_start = 1'b1;
    18. always@(posedge clk)
    19. begin
    20. TxD_start <= 1'b1;
    21. if(count < 4) begin
    22. TxD_data <= 8'hAB; end
    23. else begin
    24. TxD_data <= 8'hCD; end
    25. end
    26. always@(posedge clk)
    27. begin
    28. count <= count + 1;
    29. end
    30. endmodule
    RRITESH KAKKAR likes this.
  2. djsfantasi

    AAC Fanatic!

    Apr 11, 2010
    Could it be possible that your loop condition has cleared at the end of the first loop? Then, your variable count would not get incremented in the second loop. Count could never reach 4 and only 0xAB would be output.

    I do not know why you coded it this way, but I would expect count to be incremented at the end of the first loop.

    Senior Member

    Jun 29, 2010
    You know Verilog code also?
  4. Shankdeep Mukerji

    Thread Starter New Member

    Dec 22, 2015
    From the simulation dump, I can see that the count is getting incremented everytime from 0 to 7. What I do not understand is that how is the data getting displayed on the terminal, on what basis? I am generating data at 50 MHz and baud rate is 9600 bps, so is there data loss?

    Also, there is not much significance of count. I just put it to check how the communication is happening.
  5. JWHassler

    Active Member

    Sep 25, 2013
    This guy has useful, understandable Verilog UART code.
    And, once you understand it, you might want to switch your external UART for an FTDI FT245R.
    When you figure out the handshaking, you can communicate with the FPGA at 8+MB/sec