Hi,
I have started learning about RISC-V "architecture" and stumbled over the "byte-oriented memory" thing.
Lets imagine that we want to design a 32 bit CPU with RISC-V ISA and we want the memory to be made out of smaller memory chips (8bits wide). Normally for this scenario, i would put four of the memory chips beside each other, connect all the coresponding adress lines together and so we have a 32 bit ouput.

But with byte-oriented memory layout, the only thing that has come to my mind is that we would need to put before each memory chip an adder (if adress would be Z that on first chip we would have Z, on the second Z+1,third would be Z+2 and last one is Z+3). But from my perspective this would be so ineffective, because we would use an 1/4 of each memory chip. And if we would put all the date behind in same memory ( Z0|Z1|Z2|Z3 ) to pull all the data, we would waste an awful lot of clock cycles and it would become an 8 bit system.

I understand the advantages of byte-oriented adressing, but cannot imagine the way how it would be implemented. Can someone help?
Thanks.

 

Use 4 chips per word. CPU address bits A2....An go to A0...A(n-2) on each chip. Bits A1 and A0 go to decoder logic to determine the chip select.

 

Thank you, that makes sence, but (If i understand that correctly) and we will built it as you suggested: A0-A1 to decoder and chip select, other bits as adress bits for the memory chips and so on...
we will end up with something, that looks like this: (in the most basci form)
But with this settup we will require clock cycle for every byte of the word and fetching new value and this would became practically an 8 bit system.
What is the point i am missing here?

 

Use 4 chips per word. CPU address bits A2....An go to A0...A(n-2) on each chip. Bits A1 and A0 go to decoder logic to determine the chip select.

Well yes, but...
(see in post below)