In a colpitts oscillator, such as this one from wps.prenhall.com:

there is no collector resistor. Instead there's a collector inductor, which is a short at DC. The inductor blocks the oscillating signal from the supply line, but what about the CE amplifier you see here with respect to DC? Why is the transistor not being overpowered by a very small resistance connection from collector to Vcc? My guess is that the RFC provides little, but enough resistance, as a low Q inductor would have at least some resistance, but that's not all that fulfilling. Really appreciate any help! Thanks

 

The DC current is limited by the emitter resistor RE. Normally an RF amplifier or oscillator is biased away from the midpoint of the load line and operates class C. That means it conducts for less than half a cycle. Without actual component values it is difficult to know what the designer intended. Also note that the emitter is at RF ground by virtue of the bypass capacitor in parallel with RE.

With values for R1 and R2, I can tell you where the Q point will be.

 

I'm just getting the theoretical stuff for colpitts oscillators down right now, so setting component values aside, how is the DC emitter current determined in this circuit? I tried simulating the same biasing scheme, sans AC components, and I get voltages on the base that are actually lower than the voltage divider I put in should be giving me. For example, two 100k resistors get me 4.79V even though they're connected to the 12V source. The transistor is a 2N3904 and the emitter resistor is 1k. Any ideas? Simulated in Multisim

 

The base side is loading your voltage divider. The base current must be of the order
(6-4.79)/50 [mA] = .0242 mA=24.2uA

 

That's exactly right. Where does the 50 come from? In fact, could you explain the idea of loading a voltage divider in more detail for me?

 

The '50' is the Thevenin equivalent resistance of the voltage divider in kilohms - hence the relationship giving a result in mA.
Any current load you draw from a voltage divider must pull the unloaded voltage divider output to a lower value.
Suppose you take your 100k/100k divider with a 12V supply. You expect the voltage divider output to be 6V. Now connect a 100k load from the voltage divider output to the common supply point - effectively in parallel with the lower 100k divider resistor. Your voltage divider now looks like a 100k/50k divider with a 12V supply. The divider output would have dropped from 6V to 4V.
Suppose you change the two divider resistors from 100k to 1k each. The unloaded divider output is still 6V. Now connect the 100k load as before. The loaded divider output now only drops to 5.97V.

 

It may be worth noting that the oscillator topology looks like it will operate in Class A mode - as indicated by the DC bias arrangement. But this may not guarantee the steady-state operation of the transistor will be Class A mode with oscillation established - it may well 'relax' to a steady-state Class C operating mode with the base-emitter junction biased beyond cut-off. The RF output signal will be reasonably sinusoidal but the collector current may comprise highly non-sinusoidal current pulses at the oscillation frequency.
You may even "observe" this in the simulation of the circuit. I have actually observed this in practice when testing Colpitts RF oscillators I have built.

 

I've heard of the sliding class-c bias but still I don't have a concrete reasoning for why it "relaxes"? I have been only studying small-signal amplifiers for the past couple months, power amplifiers I've dealt with before but never had a great grasp on them. As well, where does the filtering occur? If the collector current is so highly distorted, when is that one desired frequency selected? Or am I missing something

 

"where does the filtering occur"
In the tank circuit. c1,c2,L

 

c1,c2,L form a "Pi" filter, which is tuned to the resonant frequency of the oscillator.

 

There's more than the matter of simple tuning for that particular topology. There needs to be a sufficient (360 deg) phase shift around the complete signal path loop, including the feedback. The "Pi" network notionally provides 180 degree phase shift at the oscillation frequency, which in conjunction with the CE stage base-to-collector signal inversion, provides the complete phase shift. Also the capacitors form a voltage divider whereby the the feedback voltage can be suitability proportioned to produce the overall loop gain which can sustain oscillation.

 

There's more than the matter of simple tuning for that particular topology. There needs to be a sufficient (360 deg) phase shift around the complete signal path loop, including the feedback. The "Pi" network notionally provides 180 degree phase shift at the oscillation frequency, which in conjunction with the CE stage base-to-collector signal inversion, provides the complete phase shift. Also the capacitors form a voltage divider whereby the the feedback voltage can be suitability proportioned to produce the overall loop gain which can sustain oscillation.

Whew! That's a mouthful!