Hi,

I'm still not counting on a 1 mill bleed current off a 100 mike cap causing appreciable ripple, certainly not as much as 1.2 volts. With 10 mikes, maybe. But I think the 100 mike cap will charge right up to peak.

The current is closer to 10mA. I think this will make you rethink things, but just in case, here's the math. If you assume the load is constant current (which you are), the simplified version is


V(ripple)=IT/C
V(ripple=.01*.02/1e-4
V(ripple)=2V

Simulation shows ripple is lower (about 1.5V p-p), due to the fact that the peak voltage is slightly less than 10, the current is not constant, and, more importantly, the discharge ramp is intercepted by a sinusoid.

 

Hi,

Would apologize louder, but pedal appendage is blocking mouth.

 

The circuit he is describing is similar to the one the user cherry had inquired previously.

This must be a common assignment.

 

Hi,

Would apologize louder, but pedal appendage is blocking mouth.

Beenthere, done that.

Is that a pun?

 

This is possible depending on the sophistication of the simulation models being used.



If you had an ideal voltage source, resistors of equal value, and op-amp, Vref would be 1/2 VCC dead nuts. Since practical op-amps have a minute input bias current that will cause a small voltage drop across R1. This voltage drop will cause unsymetrical readings in your divider circuit. I would imagine they would be quite small since input bias current is in the nA to fA range (FET inputs). I did not look at the 741's input bias spec so it could be worse;i.e., uA range.

If you use KCL on RonH's circuit, you will develop the equation:

0 = (Vcc-Vref)/R1 - Vref/R2 - Ibias

Solving for Vref, you will find:

Vref = (Vcc - IbiasR1)(R2/(R1+R2))



A poor voltage source. Noisy and unregulated possibly. Stay away from ripple. Use batteries.

Have you taken a look at my circuit drawing? I didn't use resistors to get the Vref. So is the Ibias still a problem?

When I'm supplying -8.8 V into the negative input of opamp, wouldn't there be some noise? Does this noise cause -8.8V to be accepted by op amp as e.g. -8.7V or -8.9V?

 

The current is closer to 10mA. I think this will make you rethink things, but just in case, here's the math. If you assume the load is constant current (which you are), the simplified version is


V(ripple)=IT/C
V(ripple=.01*.02/1e-4
V(ripple)=2V

Simulation shows ripple is lower (about 1.5V p-p), due to the fact that the peak voltage is slightly less than 10, the current is not constant, and, more importantly, the discharge ramp is intercepted by a sinusoid.

Are you referring to the current through RC load? Its average value is -8.740mA, is this fact relevant?

 

Have you taken a look at my circuit drawing? I didn't use resistors to get the Vref. So is the Ibias still a problem?

Your circuit drawing has R3, R4, R5 and R6 developing -8.8V, which I assume is Vref, at the inverting pin of the op amp. I don't understand why you say you didn't use resistors to get the Vref.
With the low values of resistance in your circuit, Ibias will be totally insignificant compared to resistor tolerances.

When I'm supplying -8.8 V into the negative input of opamp, wouldn't there be some noise? Does this noise cause -8.8V to be accepted by op amp as e.g. -8.7V or -8.9V?

Noise should be insignificant.

 

Are you referring to the current through RC load? Its average value is -8.740mA, is this fact relevant?

It is relevant in that it discharges the 100uF cap between cycles of the 50Hz input, giving you the waveform that you are attempting to convert into a square wave.
The circuit looks fine as drawn. Are you having problems with it, or do you need to add something to the op amp output? Your original question hinted at this.

 

It is relevant in that it discharges the 100uF cap between cycles of the 50Hz input, giving you the waveform that you are attempting to convert into a square wave.
The circuit looks fine as drawn. Are you having problems with it, or do you need to add something to the op amp output? Your original question hinted at this.

I have actually finished the necessary design and construction. I'm left only with writing the report. I need to substantiate the discrepancies between the results in simulation and real world.